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    • 9. 发明授权
    • Memory control device and semiconductor processing apparatus
    • 存储器控制装置和半导体处理装置
    • US08397036B2
    • 2013-03-12
    • US13406262
    • 2012-02-27
    • Rintaro ImaiSatoshi Nakano
    • Rintaro ImaiSatoshi Nakano
    • G06F13/20
    • G06F13/1689
    • The present invention provides a memory control device and a semiconductor processing apparatus which can be flexibly made adapted to a plurality of kinds of semiconductor memories. An SDRAM controller has: a register unit to which a command to be issued and a minimum interval (wait time) between issue of the command and issue of the next command are written by a CPU; and a command issuing unit that stops issue of the next command until the minimum interval written in the register elapses since issue of the command written in the register. Therefore, by changing software for the CPU, the SDRAM controller can be flexibly adapted to a plurality of kinds of SDRAMs.
    • 本发明提供一种能够灵活地适应于多种半导体存储器的存储器控​​制装置和半导体处理装置。 SDRAM控制器具有:由CPU写入发出命令和发出下一个命令的最小间隔(等待时间)的寄存器单元; 以及一个命令发布单元,直到写入寄存器中的命令发出后,停止发出下一个命令直到写入寄存器的最小间隔过去。 因此,通过改变CPU的软件,可以将SDRAM控制器灵活地适应于多种SDRAM。