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1. 发明授权

US5243687A Fuzzy computer system having a fuzzy inference processing circuit for controlling and adapting output signal to the set membership signal 失效
标题翻译：具有用于控制和适配输出信号到设置成员信号的FUZZY INFERENCE处理电路的FUZZY计算机系统
公开(公告)号：US5243687A
公开(公告)日：1993-09-07
申请号：US406961
申请日：1989-09-13
申请人： Tanichi Ando , Kazuaki Urasaki
发明人： Tanichi Ando , Kazuaki Urasaki
IPC分类号： G06N7/04
CPC分类号： G06N7/043 , Y10S706/90
摘要： A fuzzy computer system has: a digital processor; a digital memory; a fuzzy inference processing circuit; and an interface for the fuzzy inference processing circuit. The digital memory stores programs executed by the digital processor and inference rules used by the fuzzy inference processing circuit. The fuzzy inference processing circuit executes a fuzzy inference on the basis of a given inference rule. The interface connects the digital processor and the fuzzy inference processing circuit through a bus. The digital processor gives the inference rules stored in the digital memory to the fuzzy inference processing circuit through the interface and fetches the result of the inference of the fuzzy inference processing circuit through the interface.

2. 发明授权

US4122444A Apparatus for displaying numerical value information in alternative forms 失效
标题翻译：用于以替代形式显示数值信息的装置
公开(公告)号：US4122444A
公开(公告)日：1978-10-24
申请号：US656923
申请日：1976-02-10
申请人： Kenichi Kitajima , Akira Nagano , Kazuaki Urasaki
发明人： Kenichi Kitajima , Akira Nagano , Kazuaki Urasaki
IPC分类号： G09F9/302 , G09G3/04 , G06F3/14
CPC分类号： G09G3/04 , G09F9/302
摘要： An apparatus for displaying numerical value information, comprising: a first display having a plurality of digit display positions each capable of selectively displaying one of Arabic numerals; a second display having a plurality of digit display positions each capable of selectively displaying one of Arabian language numerals; a digit timing signal generator; a first and second digit drivers responsive to said digit timing signals for enabling said digit display positions of each of said first and second displays, respectively, in a digit timing sequence; a re-circulation shift register operable responsive to said digit timing signals for storing a signal representing multi-digit numerical value information comprising a plurality of digit numeral signals each representing in a bit-coded manner a value of the numeral to be displayed in the corresponding digit display position in said displays; a first converter coupled to a predetermined digit position of said register for withdrawing in said digit timing sequence a digit numeral signal for converting it into an Arabic numeral signal for representing said digit numeral signal by the Arabic numerals so as to be commonly applied to said multi-digit display positions in said first display; and a second converter for converting the output from said first converter into an Arabian language numeral signal for representing said digit numeral signal by the Arabian language numerals so as to be commonly applied to said multi-digit display positions in said second display; whereby the numeral in the respective digit of said multi-digit numerical value information is displayed in the corresponding digit display position in said first and second displays in said digit timing sequence, by Arabic and Arabian language numerals, respectively.
摘要翻译：一种用于显示数值信息的装置，包括：第一显示器，具有多个数字显示位置，每个显示位置能够选择性地显示阿拉伯数字之一; 具有多个数字显示位置的第二显示器，每个显示位置能够选择性地显示阿拉伯语数字之一; 数字定时信号发生器; 响应于所述数字定时信号的第一和第二数字驱动器，分别以数字定时序列启用所述第一和第二显示器中的每一个的所述数字显示位置; 再循环移位寄存器，用于响应于所述数字定时信号，用于存储表示多位数字信号的信号，所述多位数值信息包括多个数字数字信号，每个数字数字信号以比特编码的方式表示要显示在相应的数字中的数字的值所述显示器中的数字显示位置; 耦合到所述寄存器的预定数字位置的第一转换器，用于以所述数字定时序列取出数字数字信号，用于将其转换为阿拉伯数字信号，用于通过阿拉伯数字表示所述数字数字信号，以便被普遍应用于所述多个在所述第一显示器中显示位数; 以及第二转换器，用于将来自所述第一转换器的输出转换成阿拉伯语数字信号，用于通过阿拉伯语数字表示所述数字数字信号，以便被共同地应用于所述第二显示器中的所述多位显示位置; 由此所述多位数值信息的相应数字中的数字以所述数字定时序列分别由阿拉伯数字和阿拉伯语数字显示在所述第一和第二显示器的相应数字显示位置。

3. 发明授权

US5566274A Method and apparatus for setting membership functions, and method and apparatus for analyzing same 失效
标题翻译：用于设置隶属函数的方法和装置，以及用于分析它们的方法和装置
公开(公告)号：US5566274A
公开(公告)日：1996-10-15
申请号：US768939
申请日：1991-12-17
申请人： Tsutomu Ishida , Kazuaki Urasaki
发明人： Tsutomu Ishida , Kazuaki Urasaki
IPC分类号： G05B13/02 , G06F9/44 , G06N5/04 , G06N7/04
CPC分类号： G05B13/0275 , G06N5/048 , G06N7/04
摘要： A check is made to determine whether there is identity among set membership functions, different numbers are assigned to mutually different membership functions, and identical numbers are assigned to membership functions which are mutually identical. These membership functions are stored in memory in correlation with their numbers, labels and the names of input or output variables.
摘要翻译： PCT No.PCT / JP90 / 00529 Sec。 371 1991年12月17日第 102（e）日期1991年12月17日PCT提交1990年4月24日PCT公布。出版物WO90 / 13868 日期1990年11月15日进行检查以确定集合隶属函数之间是否存在身份，将不同的数字分配给相互不同的隶属函数，并将相同的数字分配给相互相同的隶属函数。这些隶属函数与它们的数字，标签和输入或输出变量的名称相关联地存储在存储器中。

4. 发明授权

US4051471A Key input means providing common key identifying and display driving digit timing signals 失效
标题翻译：提供公共密钥识别和显示驱动数字时序信号的主要输入方式
公开(公告)号：US4051471A
公开(公告)日：1977-09-27
申请号：US528321
申请日：1974-11-29
申请人： Isao Hatano , Akira Nagano , Kazuaki Urasaki
发明人： Isao Hatano , Akira Nagano , Kazuaki Urasaki
IPC分类号： H03M11/20 , G06F3/023 , G06F3/02
CPC分类号： G06F3/023
摘要： A keying input apparatus is provided which includes; a bit pattern generator responsive to a clock signal for generating different bit patterns of four bits, in a bit sequence and a decoding matrix for converting the different bit patterns at every fourth bit, into individual digit timing signals. A plurality of key switches are connected at one end thereof with corresponding ones of the digit timing signals and connected to a common terminal at the other ends thereof, to drive a gate responsive to the common connected output of said key switches for allowing a coded signal representative of a particular depressed key to be withdrawn from the bit pattern generator and transfer it to a circulation register for storing the coded signal. Depression of a given key thus enables the gate at a corresponding digit timing to load a coded signal corresponding to that digit timing in the register, so that the coded signal as stored in the register uniquely identifies the depressed key.

5. 发明授权

US3950743A Keying input apparatus having a reduced number of output terminals 失效
标题翻译：具有输出端子数量减少的关键输入装置
公开(公告)号：US3950743A
公开(公告)日：1976-04-13
申请号：US456817
申请日：1974-04-01
申请人： Isao Hatano , Akira Nagano , Kazuaki Urasaki
发明人： Isao Hatano , Akira Nagano , Kazuaki Urasaki
IPC分类号： G06F15/02 , G06F3/023 , G09G3/10 , H03M11/20 , G09F9/32
CPC分类号： H03M11/20 , G09G3/10
摘要： A keying input apparatus operates as a function of two kinds of timing signals, one being of a first timing period and generally composed of a plurality of digit timing signals generated in a digit sequence and the other being of a second timing period for disabling a display device during that period, such that a plurality of pieces of information, such as the digit timing signals and/or segment selection signals for the display device, are provided from a plurality of output terminals during said first timing signal for the purpose of outputting thereof to the display device, and a plurality of different coded signals, each composed of a plurality of bits, in a bit sequence, are provided from the same said plurality of output terminals during said second timing signal, each of which output terminals is individually connected to a corresponding one of a plurality of key switches, which are commonly connected through a common terminal to a register, so that any desired coded signal, as selected by a corresponding one of said plurality of key switches, can be inputted to the register during the second timing period.

6. 再颁专利

USRE36421E Fuzzy controller for selecting an input signal 失效
标题翻译：用于选择输入信号的模糊控制器
公开(公告)号：USRE36421E
公开(公告)日：1999-11-30
申请号：US751950
申请日：1996-11-19
申请人： Yutaka Ohtsubo , Kazuaki Urasaki , Yoshiro Tasaka , Atushi Hisano
发明人： Yutaka Ohtsubo , Kazuaki Urasaki , Yoshiro Tasaka , Atushi Hisano
IPC分类号： G05B13/02 , G06F9/44 , G06N7/02 , G06N7/04
CPC分类号： G06N7/043 , G05B13/0275 , G06N7/023 , Y10S706/90
摘要： In a fuzzy controller comprising a fuzzy inference device for subjecting one or a plurality of input signals to fuzzy inference operations using membership functions in accordance with a predetermined rule and outputting a non-fuzzy value determined on the basis of the results of the inferences, there are provided an input signal level converter for converting signal levels of the input signals on the input side of the fuzzy inference device and an output signal level converter for converting a signal level of the output signal on the output side of the fuzzy inference device.
摘要翻译：一种模糊控制器，包括：模糊推理装置，用于根据预定规则使用隶属度函数对一个或多个输入信号进行模糊推理操作，并输出基于推理结果确定的非模糊值，设置有用于转换模糊推理装置的输入侧的输入信号的信号电平的输入信号电平转换器和用于转换模糊推理装置的输出侧的输出信号的信号电平的输出信号电平转换器。

7. 发明授权

US5524251A Microcomputer having ALU performing min and max operations 失效
标题翻译：具有ALU的微型计算机执行最小和最大操作
公开(公告)号：US5524251A
公开(公告)日：1996-06-04
申请号：US548571
申请日：1990-07-05
申请人： Kazuaki Urasaki
发明人： Kazuaki Urasaki
IPC分类号： G06F7/02 , G06F9/30 , G06F9/302 , G06F9/44 , G06F17/18 , G06N7/02 , G06F17/10
CPC分类号： G06F9/3001 , G06F17/18 , G06F9/30021
摘要： All data to be compared are stored in a register group (1) in advance. When a MIN operation is executed, a maximum value (e.g, FF) is initially set in a memory (2). Source data outputted by the register group (1) and destination data outputted by the memory (2) are applied to a full adder/subtractor (30) operating as a subtractor. The subtractor (30) outputs a borrow signal when an item of source data is smaller than an item of destination data. In response to the borrow signal, an AND gate (33) is enabled, so that the item of source data is written in the memory (2) as a new item of destination data. When an item of source data is equal to or greater than an item of destination data, the borrow signal is not delivered as an output, the AND gate (33) is disabled and a new item of data is not stored in the memory (2). The foregoing operation is repeated with regard to all data in the register group (1). Eventually, a state is attained in which the smallest item of data among the data in the register group (1) is stored in the memory (2).In a MAX operation, a minimum value (e.g, OO) is set in the memory (2) as initial data. When the borrow signal is not outputted, the AND gate (33) is enabled. Eventually, a state is attained in which the largest item of data among the data in the register group (1) is stored in the memory (2).
摘要翻译：要比较的所有数据预先存储在寄存器组（1）中。当执行MIN操作时，在存储器（2）中初始设置最大值（例如FF）。由寄存器组（1）输出的源数据和由存储器（2）输出的目标数据被施加到作为减法器操作的全加器/减法器（30）。当源数据项目小于目的地数据项时，减法器（30）输出借位信号。响应于借位信号，使能门（33），使源数据项作为目的地数据的新项目写入存储器（2）。当源数据项目等于或大于目的地数据项时，借位信号不作为输出传送，与门禁止（33），新的数据项目不存储在存储器（2）中）。关于寄存器组（1）中的所有数据重复上述操作。最终，达到将寄存器组（1）中的数据中的最小数据项存储在存储器（2）中的状态。在MAX操作中，在存储器（2）中将最小值（例如，OO）设置为初始数据。当不输出借位信号时，与门（33）被使能。最终，达到将寄存器组（1）中的数据中的最大数据项存储在存储器（2）中的状态。

8. 发明授权

US5367610A Fuzzy controller for selecting an input signal 失效
标题翻译：用于选择输入信号的模糊控制器
公开(公告)号：US5367610A
公开(公告)日：1994-11-22
申请号：US412936
申请日：1989-09-26
申请人： Yutaka Ohtsubo , Kazuaki Urasaki , Yoshiro Tasaka , Atushi Hisano
发明人： Yutaka Ohtsubo , Kazuaki Urasaki , Yoshiro Tasaka , Atushi Hisano
IPC分类号： G05B13/02 , G06F9/44 , G06N7/02 , G06N7/04
CPC分类号： G06N7/043 , G05B13/0275 , G06N7/023 , Y10S706/90
摘要： In a fuzzy controller comprising a fuzzy inference device for subjecting one or a plurality of input signals to fuzzy inference operations using membership functions in accordance with a predetermined rule and outputting a non-fuzzy value determined on the basis of the results of the inferences, there are provided an input signal level converter for converting signal levels of the input signals on the input side of the fuzzy inference device and an output signal level converter for converting a signal level of the output signal on the output side of the fuzzy inference device.
摘要翻译：一种模糊控制器，包括：模糊推理装置，用于根据预定规则使用隶属度函数对一个或多个输入信号进行模糊推理操作，并输出基于推理结果确定的非模糊值，设置有用于转换模糊推理装置的输入侧的输入信号的信号电平的输入信号电平转换器和用于转换模糊推理装置的输出侧的输出信号的信号电平的输出信号电平转换器。

9. 发明授权

US4128756A Count control apparatus 失效
标题翻译：计数控制装置
公开(公告)号：US4128756A
公开(公告)日：1978-12-05
申请号：US800714
申请日：1977-05-26
申请人： Akira Nagano , Kazuaki Urasaki , Akira Osato , Isao Sakurai
发明人： Akira Nagano , Kazuaki Urasaki , Akira Osato , Isao Sakurai
IPC分类号： B41L3/00 , G01D1/04 , G01D1/18 , G03G21/00 , G03G21/02 , G06M1/00 , G06M7/00 , G06M7/06 , G06M3/02
CPC分类号： G03G21/02
摘要： A count control apparatus for controlling a photocopying machine is constructed to be enabled by a copy command signal to effect repetitive photocopying operations and to generate a sheet number pulse for each photocopying operation wherein a desired number of sheets being photocopied by said photocopying machine is preset by a keyboard or the like. The sheet number pulses are counted, the preset number is compared with the count number, and the copy command signal is generated in response to a comparison of the count value with the preset value. Normally the copy command signal is conditioned by a comparison of the count number with the preset number. However the copy command signal is prevented from being conditioned by the comparison in response to a manual changing of the presetting whereby the copy command signal is conditioned in a different manner during the changing of the presetting, whereby a differently conditioned copy command signal is provided. After the preset number is changed manually to a new desired preset number, the copy command signal is again conditioned by said comparison but responsive to the manual completion of the presetting change mode.
摘要翻译：用于控制复印机的计数控制装置被构造成能够通过复印命令信号实现重复的复印操作，并且为每个复印操作生成纸张数脉冲，其中由所述复印机复印的期望数量的纸张由键盘等。计数纸张数脉冲，将预设编号与计数值进行比较，并且响应于计数值与预设值的比较而产生复印命令信号。通常，复制命令信号通过计数数与预设数的比较来调节。然而，通过响应于手动改变预设的比较来防止复制命令信号被调节，由此在改变预置期间以不同的方式对复制命令信号进行调节，从而提供不同的条件的复制命令信号。在将预设号码手动改变为新的期望预置号码之后，复制命令信号再次由所述比较调节，但是响应于手动完成预设改变模式。

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