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1. 发明授权

US08422270B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08422270B2
公开(公告)日：2013-04-16
申请号：US13044892
申请日：2011-03-10
申请人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
发明人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C2013/0045 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
摘要翻译：非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路，每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

2. 发明申请

US20110228586A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110228586A1
公开(公告)日：2011-09-22
申请号：US13044892
申请日：2011-03-10
申请人： Suguru KAWABATA , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
发明人： Suguru KAWABATA , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C2013/0045 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
摘要翻译：非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路，每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

3. 发明授权

US08482956B2 Semiconductor memory device and method of driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482956B2
公开(公告)日：2013-07-09
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

4. 发明申请

US20120014163A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20120014163A1
公开(公告)日：2012-01-19
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

5. 发明授权

US08411488B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08411488B2
公开(公告)日：2013-04-02
申请号：US13233301
申请日：2011-09-15
申请人： Suguru Kawabata , Shinobu Yamazaki , Kazuya Ishihara , Junya Onishi , Nobuyoshi Awaya , Yukio Tamai
发明人： Suguru Kawabata , Shinobu Yamazaki , Kazuya Ishihara , Junya Onishi , Nobuyoshi Awaya , Yukio Tamai
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/79
摘要： A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，用于存储通过布置存储单元而提供的用户数据，每个存储单元具有可变电阻元件，该可变电阻元件具有第一电极，第二电极和夹在第一和第二电极之间的金属氧化物制成的可变电阻器。第一和第二电极由与可变电阻器形成欧姆结的导电材料和分别与可变电阻器形成非欧姆结的导电材料形成。可变电阻器通过在电极之间施加电压而在两个或多个不同的电阻状态之间变化。改变后的电阻状态保持非挥发性。在存储单元阵列用于存储用户数据之前，将存储单元阵列中的所有存储单元的可变电阻元件设置为处于未使用状态的两个或多个不同电阻状态中的最高值。

6. 发明授权

US08120944B2 Control circuit for forming process on nonvolatile variable resistive element and control method for forming process 有权
标题翻译：用于在非易失性可变电阻元件上形成工艺的控制电路和用于形成工艺的控制方法
公开(公告)号：US08120944B2
公开(公告)日：2012-02-21
申请号：US12722851
申请日：2010-03-12
申请人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
发明人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/24
摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.
摘要翻译：非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成，要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线检测到。

7. 发明申请

US20100232209A1 CONTROL CIRCUIT FOR FORMING PROCESS ON NONVOLATILE VARIABLE RESISTIVE ELEMENT AND CONTROL METHOD FOR FORMING PROCESS 有权
标题翻译：用于形成非易失性电阻元件的控制电路和控制方法
公开(公告)号：US20100232209A1
公开(公告)日：2010-09-16
申请号：US12722851
申请日：2010-03-12
申请人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
发明人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/24
摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.
摘要翻译：非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成，要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线检测到。

8. 发明授权

US08530877B2 Non-volatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US08530877B2
公开(公告)日：2013-09-10
申请号：US13182696
申请日：2011-07-14
申请人： Junya Onishi , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya Onishi , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

9. 发明申请

US20120025163A1 NON-VOLATILE SEMICONDUCTOR DEVICE 有权
标题翻译：非挥发性半导体器件
公开(公告)号：US20120025163A1
公开(公告)日：2012-02-02
申请号：US13182696
申请日：2011-07-14
申请人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

10. 发明申请

US20120075909A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120075909A1
公开(公告)日：2012-03-29
申请号：US13212457
申请日：2011-08-18
申请人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/79
摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.
摘要翻译：提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

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