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1. 发明公开

EP1246231A2 Electrode materials with improved hydrogen degradation resistance and fabrication method 有权
标题翻译： Elektrodenmaterial mit verbicultem Wasserstoffdegradationswiderstand und Herstellungsmethode
公开(公告)号：EP1246231A2
公开(公告)日：2002-10-02
申请号：EP02006830.0
申请日：2002-03-25
申请人： Sharp Kabushiki Kaisha
发明人： Zhang, Fengyan , Li, Tingkai , Ying, Hong , Ono, Yoshi , Hsu, Sheng Teng
IPC分类号： H01L21/02
CPC分类号： H01L28/75 , H01L21/31604 , H01L21/31683 , H01L28/55
摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer, and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing atop electrode on the ferroelectric layer, including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing a structure obtained by above describe steps in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要翻译：用于铁电体器件的电极包括底部电极; 形成在强电介质层上并由金属组合形成的顶电极，所述金属包括从由铂和铱组成的金属组中的第一金属取向，以及从由铝组成的金属组中的第二金属和钛; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极，包括同时沉积从由铂和铱组成的金属组中取得的第一金属; 和从由铝和钛组成的金属组中夺取的第二金属; 以及通过在氧气氛中退火通过上述步骤获得的结构形成钝化层，以在顶部电极上形成氧化物钝化层。

2. 发明公开

EP1124262A3 Multilayer dielectric stack and method 有权
标题翻译：介电层复合材料和方法
公开(公告)号：EP1124262A3
公开(公告)日：2002-10-09
申请号：EP01301136.6
申请日：2001-02-08
申请人： Sharp Kabushiki Kaisha
发明人： Ma, Yanjun , Ono, Yoshi
IPC分类号： H01L29/51 , H01L21/28 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

3. 发明公开

EP1049147A2 Epitaxially grown lead germanate film 审中-公开
标题翻译： Epitaktisch gewachsener Bleigermanat电影
公开(公告)号：EP1049147A2
公开(公告)日：2000-11-02
申请号：EP00303598.7
申请日：2000-04-28
申请人： SHARP KABUSHIKI KAISHA
发明人： Li, Tingkai , Zhang, Fengyan , Ono, Yoshi , Hsu, Sheng Teng
IPC分类号： H01L21/316
CPC分类号： H01L21/31604 , C23C16/40 , H01L21/31691 , Y10S438/933
摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb 5 Ge 3 O 11 thin films along with c-axis orientation.
摘要翻译：本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。这些外延铁电体已经应用于FeRAM存储器件中。本发明的沉积方法外延地生长铁电Pb5Ge3O11薄膜以及c轴取向。

4. 发明公开

EP1498945A2 Low power flash memory cell and method 审中-公开
标题翻译： Niederleistungsaufnahme-FLASH-Speicherzelle und Verfahren
公开(公告)号：EP1498945A2
公开(公告)日：2005-01-19
申请号：EP04016720.7
申请日：2004-07-15
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Ono, Yoshi
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883 , Y10S438/975
摘要： Flash memory cells are provided with a high-k dielectric material interposed between a floating polysilicon gate and a control gate. A tunnel oxide layer is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided, comprising the steps of: forming a first polysilicon layer over a substrate, forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer, depositing a second polysilicon layer over the oxide layer, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, the exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
摘要翻译：闪存单元设置有介于浮置多晶硅栅极和控制栅极之间的高k电介质材料。隧道氧化物层介于浮置多晶硅栅极和衬底之间。还提供了形成闪速存储器单元的方法，包括以下步骤：在衬底上形成第一多晶硅层，形成通过第一多晶硅层并进入衬底的沟槽，以及用氧化物层填充沟槽，沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部在第一多晶硅层的底部之上，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅层的顶部。然后可以使用CMP工艺对所得到的结构进行平面化。然后可以在第一多晶硅层上沉积高k电介质层。然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。在图案化期间，暴露的第二多晶硅层被蚀刻。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。可以对高k电介质层进行图案化，以结合形成闪存单元的过程形成非存储晶体管。

5. 发明公开

EP1249865A2 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 审中-公开
标题翻译：葛兰素史克（Kelfer-Zwischenverbindungen）
公开(公告)号：EP1249865A2
公开(公告)日：2002-10-16
申请号：EP02006940.7
申请日：2002-03-26
申请人： Sharp Kabushiki Kaisha
发明人： Pan, Wei , Ono, Yoshi , Evans, David Russell , Hsu, Sheng Teng
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
摘要翻译：通过原子层化学气相沉积（ALCVD）在衬底上沉积多层阻挡金属薄膜。多层膜可以包括单个化学物种的几个不同层，或者各个不同的或交替的化学物质（12,26）的几个层。在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。整个多层膜的厚度可以是大约50埃。当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和阶梯覆盖。本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

6. 发明授权

EP1124262B1 Integrated circuit comprising a multilayer dielectric stack and method 有权
标题翻译：用介电层复合材料和方法的一个集成电路
公开(公告)号：EP1124262B1
公开(公告)日：2006-04-19
申请号：EP01301136.6
申请日：2001-02-08
申请人： SHARP KABUSHIKI KAISHA
发明人： Ma, Yanjun , Ono, Yoshi
IPC分类号： H01L29/51 , H01L21/28 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583

7. 发明公开

EP1139405A3 Method for improving electrical properties of high dielectric constant films 审中-公开
标题翻译：方法，以改善膜的具有高介电常数的电性能
公开(公告)号：EP1139405A3
公开(公告)日：2004-01-28
申请号：EP01302880.8
申请日：2001-03-28
申请人： SHARP KABUSHIKI KAISHA
发明人： Ma, Yanjun , Ono, Yoshi
IPC分类号： H01L21/316 , H01L21/28
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31155 , H01L21/31604 , H01L21/31691 , H01L29/517
摘要： A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.

8. 发明公开

EP1249865A3 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 审中-公开
标题翻译：用于通过ALCVD沉积的铜互连多层金属薄膜的阻挡层
公开(公告)号：EP1249865A3
公开(公告)日：2004-01-02
申请号：EP02006940.7
申请日：2002-03-26
申请人： Sharp Kabushiki Kaisha
发明人： Pan, Wei , Ono, Yoshi , Evans, David Russell , Hsu, Sheng Teng
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species (12,26). In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

9. 发明公开

EP1139405A2 Method for improving electrical properties of high dielectric constant films 审中-公开
标题翻译：方法，以改善膜的具有高介电常数的电性能
公开(公告)号：EP1139405A2
公开(公告)日：2001-10-04
申请号：EP01302880.8
申请日：2001-03-28
申请人： SHARP KABUSHIKI KAISHA
发明人： Ma, Yanjun , Ono, Yoshi
IPC分类号： H01L21/316
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31155 , H01L21/31604 , H01L21/31691 , H01L29/517
摘要： A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.
摘要翻译：通过初始膜的沉积和注入氧离子通过降低膜的氧缺陷，同时减少或消除形成的界面的二氧化硅层的修改的薄膜改善高介电常数膜的电特性的方法。初始高介电常数材料被沉积在通过CVD，反应性溅射或蒸发的方式的硅衬底。氧离子在使用虽然因此，提供的其它方法等离子体离子浸没（PIII）优选植入。植入后的基板进行退火，以调节所述高介电常数成膜。

10. 发明公开

EP1124262A2 Multilayer dielectric stack and method 有权
标题翻译： Integrierte Schaltung mit einem dielektrischen Schichtverbund und Verfahren
公开(公告)号：EP1124262A2
公开(公告)日：2001-08-16
申请号：EP01301136.6
申请日：2001-02-08
申请人： Sharp Kabushiki Kaisha
发明人： Ma, Yanjun , Ono, Yoshi
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.
摘要翻译：提供了具有高k材料和插入材料的交替层的多层电介质叠层。插入材料的存在和高k材料层的薄度即使在相对高的退火温度下也降低或消除了高k材料内的结晶效应。高k电介质层是优选锆或铪的金属氧化物。插层优选为非晶态氧化铝，氮化铝或氮化硅。因为这些层减少了单个层内晶体结构的影响，因此整个隧穿电流降低。还提供了作为沉积用于形成上述多层电介质叠层的所需材料的方法的原子层沉积，溅射和蒸发。

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