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1. 发明申请

US20070050601A1 Avoiding live-lock in a processor that supports speculative execution 有权
标题翻译：避免在支持推测性执行的处理器中实时锁定
公开(公告)号：US20070050601A1
公开(公告)日：2007-03-01
申请号：US11210557
申请日：2005-08-23
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Guarav Garg , Ketaki Rao
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Guarav Garg , Ketaki Rao
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3863 , G06F9/3885
摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.
摘要翻译：本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。系统接下来取消状态指示。然后，系统在正常执行模式下继续发出以程序顺序执行的指令。以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。

2. 发明授权

US07634639B2 Avoiding live-lock in a processor that supports speculative execution 有权
标题翻译：避免在支持推测性执行的处理器中实时锁定
公开(公告)号：US07634639B2
公开(公告)日：2009-12-15
申请号：US11210557
申请日：2005-08-23
申请人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
发明人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3863 , G06F9/3885
摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.
摘要翻译：本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。系统接下来取消状态指示。然后，系统在正常执行模式下继续发出以程序顺序执行的指令。以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。

3. 发明申请

US20070226472A1 Method and apparatus for sampling instructions on a processor that supports speculative execution 有权
标题翻译：用于在支持推测性执行的处理器上对指令进行采样的方法和装置
公开(公告)号：US20070226472A1
公开(公告)日：2007-09-27
申请号：US11405965
申请日：2006-04-17
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此所记录的信息可用于确定处理器的性能

4. 发明申请

US20070130451A1 Mechanism for hardware tracking of return address after tail call elimination of return-type instruction 有权
标题翻译：尾部呼叫消除返回类型指令后返回地址的硬件跟踪机制
公开(公告)号：US20070130451A1
公开(公告)日：2007-06-07
申请号：US11352147
申请日：2006-02-10
申请人： Paul Caprioli , Sherman Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman Yip , Shailender Chaudhry
IPC分类号： G06F15/00
CPC分类号： G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
摘要翻译：检测到返回类型指令的尾部消除消息后，技术维护返回地址堆栈（RAS）内容和RAS顶层（TOS）指针的对齐。在本发明的至少一个实施例中，一种装置包括处理器流水线和至少第一返回地址堆栈，用于在处理器流水线的第一级保持与指令流相关联的返回地址堆栈。响应于检测到与第一级遇到的第一呼叫类型指令相关联的一个或多个指令的尾部呼叫消除序列，处理器流水线被配置为维持第一返回地址堆栈不变。否则处理器流水线被配置为将与第一调用类型指令相关联的返回地址推送到第一返回地址堆栈。

5. 发明申请

US20060168432A1 Branch prediction accuracy in a processor that supports speculative execution 审中-公开
标题翻译：支持推测执行的处理器中的分支预测精度
公开(公告)号：US20060168432A1
公开(公告)日：2006-07-27
申请号：US11042687
申请日：2005-01-24
申请人： Paul Caprioli , Sherman Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman Yip , Shailender Chaudhry
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/3844
摘要： One embodiment of the present invention provides a system which improves branch prediction accuracy in a processor that supports speculative-execution. During normal-execution mode, the system issues instructions in program order. Upon encountering a launch condition which causes a processor to enter a speculative-execution mode, the system performs a checkpoint and begins executing instructions in a speculative-execution mode. Upon encountering a branch instruction during speculative-execution mode, the system selects the subsequent instruction to be executed based on a current state of a branch predictor and does not update the current state of the branch predictor, thereby preventing the branch predictor from being incorrectly updated twice when re-executing the branch instruction after returning to normal-execution mode.
摘要翻译：本发明的一个实施例提供一种提高支持推测执行的处理器中的分支预测精度的系统。在正常执行模式下，系统以程序顺序发出指令。当遇到导致处理器进入推测执行模式的启动条件时，系统执行检查点并以推测执行模式开始执行指令。在推测执行模式期间遇到分支指令时，系统基于分支预测器的当前状态选择要执行的后续指令，并且不更新分支预测器的当前状态，从而防止分支预测器被错误地更新在返回到正常执行模式后重新执行分支指令时，两次。

6. 发明申请

US20070226465A1 Technique for executing selected instructions in order 有权
标题翻译：按顺序执行所选指令的技术
公开(公告)号：US20070226465A1
公开(公告)日：2007-09-27
申请号：US11371143
申请日：2006-03-08
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip
IPC分类号： G06F9/40
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3017 , G06F9/3838 , G06F9/3857
摘要： A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.
摘要翻译：用于协调处理器中允许指令执行无序的指令的执行的技术包括解码根据处理器的指令集定义的特定指令。然后将对应于特定指令的辅助指令序列引入到可执行操作流中。相应的助手序列包括第一人造依赖指令，其对与实际不用作特定指令执行的操作的寄存器源或目标的寄存器进行编码依赖关系。

7. 发明申请

US20050273580A1 Avoiding register RAW hazards when returning from speculative execution 有权
标题翻译：避免在从推测执行返回时注册RAW危险
公开(公告)号：US20050273580A1
公开(公告)日：2005-12-08
申请号：US11053382
申请日：2005-02-07
申请人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Sherman Yip , Marc Tremblay
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译：本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。该系统在具有按顺序架构的处理器内操作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。在操作期间，在正常执行模式下执行程序期间，系统以程序顺序发出执行指令。在发生指令（发射点指令）期间遇到使处理器进入推测执行模式的条件（发射条件）时，系统产生检查点，该检查点随后可用于将程序的执行返回到启动点指令，并以推测执行模式开始执行。当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点从启动点指令以正常执行模式恢复执行。在这样做时，系统确保在进入投机执行模式之前处于短延迟记分板中的条目，以及尚未解决的条目，以便在从启动时恢复执行时防止寄存器RAW危险，点指令。

8. 发明授权

US08484434B2 Index generation for cache memories 有权
标题翻译：高速缓存存储器的索引生成
公开(公告)号：US08484434B2
公开(公告)日：2013-07-09
申请号：US13402796
申请日：2012-02-22
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F13/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

9. 发明授权

US07610470B2 Preventing register data flow hazards in an SST processor 有权
标题翻译：防止SST处理器中的寄存器数据流危害
公开(公告)号：US07610470B2
公开(公告)日：2009-10-27
申请号：US11703462
申请日：2007-02-06
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863
摘要： One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread. While executing instructions in the deferred mode, if the speculative copy of the dependency information for a destination register indicates that a write-after-write (WAW) hazard exists with a subsequent non-deferred instruction executed by the first thread in execute-ahead mode, the system uses the second thread to execute the deferred instruction to produce a result and forwards the result to be used by subsequent deferred instructions without committing the result to the architectural state of the destination register. Hence, the system makes the result available to the subsequent deferred instructions without overwriting the result produced by a following non-deferred instruction.
摘要翻译：本发明的一个实施例提供一种在同时推测的线程中防止数据危害的系统。系统通过使用第一个线程以执行模式执行指令来启动。在执行执行模式下执行指令时，系统维护每个寄存器的依赖信息，指示寄存器是否受到未解析的数据依赖。在执行提前模式下解析数据依赖关系时，系统将依赖关系信息复制到依赖关系信息的推测性副本。然后，系统使用第二个线程以延迟模式开始执行延迟指令。在延迟模式下执行指令时，如果目的寄存器的依赖关系信息的推测性副本指示在执行提前模式下由第一线程执行的后续非延迟指令存在写后写入（WAW）危险，系统使用第二个线程执行延迟指令以产生结果，并转发后续延迟指令使用的结果，而不将结果提交到目标寄存器的体系结构状态。因此，系统使结果可用于后续延期指令，而不会覆盖由以下非延迟指令产生的结果。

10. 发明授权

US07571304B2 Generation of multiple checkpoints in a processor that supports speculative execution 有权
标题翻译：在支持推测性执行的处理器中生成多个检查点
公开(公告)号：US07571304B2
公开(公告)日：2009-08-04
申请号：US11084655
申请日：2005-03-18
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3842
摘要： One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.
摘要翻译：本发明的一个实施例提供一种在支持推测执行的处理器中创建多个检查点的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在使处理器进入执行模式的指令期间遇到启动条件时，系统执行初始检查点并以执行提前模式开始执行指令。在执行提前模式期间遇到预定义的条件时，系统生成附加检查点，并以执行提前模式继续执行指令。如果处理器随后遇到需要处理器返回到检查点的条件，则生成附加检查点将允许处理器返回到附加检查点，而不是先前检查点。

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