专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2007164787A Memory system 有权
标题翻译：记忆系统
公开(公告)号：JP2007164787A
公开(公告)日：2007-06-28
申请号：JP2006331050
申请日：2006-12-07
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE JAE-JUN , CHOI JOO-SUN , KIM KYU-HYOUN , PARK KWANG-SOO
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16
CPC分类号： G11C5/066 , G11C5/02
摘要： PROBLEM TO BE SOLVED: To provide point-to-point link between memory devices. SOLUTION: This memory system has first and second primary memories and first and second auxiliary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second auxiliary memories. A first connection element, like a connector or a soldered, one connects at least one of the other first and second primary and first and second auxiliary memories to a mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供存储器件之间的点对点链接。解决方案：该存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。诸如连接器或焊接的第一连接元件将第一和第二主要和第一和第二辅助存储器中的至少一个连接到母板。第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。存储器系统还包括存储器控制器，该存储器控制器通过点对二点链接连接到主存储器。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007124661A Clock generation circuit 有权
标题翻译：时钟发生电路
公开(公告)号：JP2007124661A
公开(公告)日：2007-05-17
申请号：JP2006291564
申请日：2006-10-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK MOON-SOOK , KIM KYU-HYOUN
IPC分类号： H03K5/00 , G06F1/10 , G11C11/4076 , H03K5/13 , H03K5/151 , H03K5/19 , H03L7/08 , H03L7/081
CPC分类号： H03K5/156 , G11C7/22 , G11C7/222 , G11C29/023 , H03L7/08 , H03L7/0812
摘要： PROBLEM TO BE SOLVED: To provide an improved clock generation circuit which is made further compact and is reduced in power consumption. SOLUTION: A semiconductor device and method comprises a duty cycle correction circuit having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate clock signals. The shared charge pump adjusts a voltage level of a control signal VC in response to corrected clock signals and provides the control signal VC to each of the amplification parts. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种改进的时钟发生电路，其进一步紧凑并且功耗降低。解决方案：半导体器件和方法包括具有共享电荷泵和多个放大部分的占空比校正电路。多个放大部分产生时钟信号。共享电荷泵响应于校正的时钟信号来调节控制信号VC的电压电平，并将控制信号VC提供给每个放大部分。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007143134A Differential amplifier, differential amplifying method, and phase locked loop and delay locked loop using the same 审中-公开
标题翻译：差分放大器，差分放大方法和相位锁定环路和延迟锁定环路
公开(公告)号：JP2007143134A
公开(公告)日：2007-06-07
申请号：JP2006293034
申请日：2006-10-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM JIN-YOUNG , KIM KYU-HYOUN
IPC分类号： H03L7/081 , H03F3/45 , H03L7/08
CPC分类号： H03F3/45183 , H03F2203/45371 , H03K5/1565 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/0996
摘要： PROBLEM TO BE SOLVED: To provide a differential amplifier which can reduce a duty cycle distortion in an output signal when it is used in a phase locked loop (PLL) or a delay locked loop (DLL). SOLUTION: The differential amplifier includes an input stage 710, a biasing unit 720 and a load unit 730. The input stage receives a first phase signal Clki and at least two phase signals Clkib, Clkibr among odd-numbered phase signals, wherein the average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal "out", "outb" based on differentially amplifying of the first phase signal and the at least two phase signals. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种差分放大器，当差分放大器用于锁相环（PLL）或延迟锁定环（DLL）时，可以减小输出信号中的占空比失真。
解决方案：差分放大器包括输入级710，偏置单元720和负载单元730.输入级在奇数相位信号中接收第一相位信号Clki和至少两个相位信号Clkib，Clkibr，其中所述至少两个相位信号的相位的平均值具有与第一相位信号基本上180度的相位差。偏压单元耦合在输入级和第一电源电压之间。负载单元耦合在输入级和第二电源电压之间，并且被配置为基于第一相位信号和至少两个相位信号的差分放大来输出差分输出信号“out”，“outb”。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007124660A Clock generating circuit and method for generating clock signals 审中-公开
标题翻译：时钟生成电路和产生时钟信号的方法
公开(公告)号：JP2007124660A
公开(公告)日：2007-05-17
申请号：JP2006291563
申请日：2006-10-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM KYU-HYOUN
IPC分类号： H03K5/15 , G06F1/04 , G06F1/06 , H03K3/03 , H03L7/06
CPC分类号： H03K3/0315 , H03K5/15033 , H03K2005/00052
摘要： PROBLEM TO BE SOLVED: To provide a clock generating circuit and method for generating clock signals. SOLUTION: A clock generating circuit comprises: an inverter which directly receives an external clock signal and generates an inverted external clock signal; M loop circuits LC 1 -LC M in which a first loop circuit receives the inverted external clock signal, each of which includes (n) nodes ((n) is a constant of ≥2), in which each of M-1 (M is a constant of ≥1) loop circuits generates (n) intermediate internal clock signal from corresponding one of the (n) nodes, and which are arrayed in series wherein a frequency of the (n) intermediate internal clock signals is a multiple of a frequency of the external clock signal and the inverted external clock signal; and (n) inverter sets each of which includes M-1 inverters connected in series to receive a corresponding intermediate internal clock signal from a previous loop circuit and to output the corresponding intermediate internal clock signal to the next loop circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种用于产生时钟信号的时钟发生电路和方法。解决方案：时钟发生电路包括：逆变器，其直接接收外部时钟信号并产生反相的外部时钟信号; 其中第一环路电路接收反相的外部时钟信号，其中每个包括（n）个节点（（n）为常数）的M个回路电路LC 1 其中M-1（M是≥1的常数）环路电路中的每一个产生（n）来自（n）个节点中的一个节点的中间内部时钟信号，并且它们串联排列，其中频率（n）个中间内部时钟信号是外部时钟信号和反相外部时钟信号的频率的倍数; 和（n）个逆变器组，每个逆变器组包括串联连接的M-1个反相器，以接收来自先前环路电路的对应的中间内部时钟信号，并将相应的中间内部时钟信号输出到下一个环路电路。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006115489A Impedance adjustment circuit, integrated circuit including the same and impedance adjustment method of output driver using the same 有权
标题翻译：阻抗调整电路，包括相同的集成电路和使用其的输出驱动器的阻抗调整方法
公开(公告)号：JP2006115489A
公开(公告)日：2006-04-27
申请号：JP2005276474
申请日：2005-09-22
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , LEE JAE-JUN , KIM KYU-HYOUN
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/0278
摘要： PROBLEM TO BE SOLVED: To provide an impedance calibration circuit, integrated circuit including the same, and impedance adjustment method of an output driver utilizing the same. SOLUTION: The present invention relates to an impedance adjustment circuit including a calibration circuit, a first register and a second register. The calibration circuit generates a reference current by supplying an internal voltage to an external resistor connected to a calibration terminal and outputs first and second calibration signals in response to the reference current, first and second reference voltages and first and second impedance control signals. The first register increases/decreases a bit value of the first impedance control signal in response to the first calibration signal. The second register increases/decreases a bit value of the second impedance control signal in response to the second calibration signal. Thus, the skew of a signal transmitted by the output driver can be decreased. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种阻抗校准电路，包括该阻抗校准电路的集成电路和使用该阻抗校正电路的输出驱动器的阻抗调节方法。阻抗调整电路技术领域本发明涉及一种包括校准电路，第一寄存器和第二寄存器的阻抗调整电路。校准电路通过向连接到校准端子的外部电阻器提供内部电压来产生参考电流，并响应于参考电流，第一和第二参考电压以及第一和第二阻抗控制信号而输出第一和第二校准信号。第一寄存器响应于第一校准信号增加/减少第一阻抗控制信号的位值。第二寄存器响应于第二校准信号增加/减少第二阻抗控制信号的位值。因此，可以减少由输出驱动器发送的信号的偏斜。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2007006492A Phase locked loop circuit and method of locking phase 有权
标题翻译：相锁闭环电路和锁相方法
公开(公告)号：JP2007006492A
公开(公告)日：2007-01-11
申请号：JP2006171573
申请日：2006-06-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK MOON-SOOK , KIM KYU-HYOUN
IPC分类号： H03L7/099 , G06F1/08 , H03K3/03 , H03K5/26
CPC分类号： H03L7/0995 , G11C7/22 , G11C7/222 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To provide a phase locked loop and method in which various high-frequency clock signals can be generated even when a power supply voltage level becomes low. SOLUTION: A phase locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase of the feedback clock signal and outputting a down signal when the phase of the external clock signal lags the phase of the feedback clock signal, a loop filter circuit increasing a control voltage in response to the up signal and decreasing the control voltage in response to the down signal, and a voltage controlled oscillator circuit receiving the control voltage and directly generating at least n (where n is an integer ≥4) internal clock signals. The phase locked loop circuit may also include a voltage controlled oscillator circuit, including at least four loops, receiving the control voltage and generating multiple internal clock signals. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供即使在电源电压变低时也能够产生各种高频时钟信号的锁相环和方法。解决方案：锁相环电路可以包括接收外部时钟信号和反馈时钟信号的相位检测器，并且当外部时钟信号的相位引导反馈时钟信号的相位并输出下降沿时输出上升信号信号，当外部时钟信号的相位滞后于反馈时钟信号的相位时，环路滤波器电路响应于上升信号增加控制电压并响应于下降信号降低控制电压，以及压控振荡器电路接收控制电压并直接产生n（其中n为整数≥4）内部时钟信号。锁相环电路还可以包括压控振荡器电路，其包括至少四个环路，接收控制电压并产生多个内部时钟信号。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2008067358A Signal processing apparatus, signal processing method, and image sensor 审中-公开
标题翻译：信号处理装置，信号处理方法和图像传感器
公开(公告)号：JP2008067358A
公开(公告)日：2008-03-21
申请号：JP2007169555
申请日：2007-06-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HAN JUNE-SOO , KIM KYU-HYOUN
IPC分类号： H04N5/335 , H04N5/357 , H04N5/363 , H04N5/374 , H04N5/378
CPC分类号： H03M1/1245
摘要： PROBLEM TO BE SOLVED: To provide a signal processing apparatus and signal processing method, capable of increasing an operation speed of a device such as an image sensor.
SOLUTION: The signal processing apparatus includes a CDS unit 31 which generates a first CDS signal from a first set of input signals generated at a predetermined node, and a conversion unit 35 which converts a second CDS signal into a respective converted signal concurrently as the CDS unit 31 generates the first CDS signal, the second signal being determined from a second set of input signals previously generated at the predetermined node.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供能够提高诸如图像传感器的装置的操作速度的信号处理装置和信号处理方法。解决方案：信号处理装置包括：CDS单元31，其从在预定节点处生成的第一组输入信号生成第一CDS信号;以及转换单元35，其将第二CDS信号同时转换为相应的转换信号当CDS单元31产生第一CDS信号时，第二信号由先前在预定节点产生的第二组输入信号确定。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007220278A Semiconductor memory device and memory system including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：JP2007220278A
公开(公告)日：2007-08-30
申请号：JP2007029753
申请日：2007-02-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , KIM KYU-HYOUN
IPC分类号： G11C29/42
CPC分类号： H03M13/29 , G06F11/08 , G06F11/1008 , G11C7/1006 , G11C29/42 , G11C2029/0411 , G11C2207/104
摘要： PROBLEM TO BE SOLVED: To disclose a semiconductor memory device and a memory system including the same. SOLUTION: The semiconductor memory device is provided with a first memory cell array block for generating first data, a second memory cell array for generating second data, a first error detection code generator for generating a first error detection code for the first data, and generating a first final error detection signal by combining a portion of bits of the first error detection code with a portion of bits of a second error detection code, and a second error detection code generator for generating a second error detection code for the second data, and generating a second final error detection signal by combining remaining bits excluding the portion of bits of the second error detection code with remaining bits excluding the portion of bits of the first error detection code. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：公开半导体存储器件和包括该半导体存储器件的存储器系统。解决方案：半导体存储器件设置有用于产生第一数据的第一存储单元阵列块，用于产生第二数据的第二存储单元阵列，用于产生第一数据的第一错误检测码的第一错误检测码产生器并且通过将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合来产生第一最终错误检测信号，以及第二错误检测码发生器，用于生成第二错误检测码的第二错误检测码数据，并且通过将排除第二错误检测码的位的部分的剩余比特与除了第一错误检测码的比特的部分之外的剩余比特来生成第二最终错误检测信号。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007018692A Data input/data output control device and method 审中-公开
标题翻译：数据输入/数据输出控制装置及方法
公开(公告)号：JP2007018692A
公开(公告)日：2007-01-25
申请号：JP2006185913
申请日：2006-07-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK MOON-SOOK , KIM KYU-HYOUN
IPC分类号： G11C11/409 , G11C11/407
CPC分类号： H03M9/00
摘要： PROBLEM TO BE SOLVED: To transfer data of m=2 n +k bits during one clock cycle. SOLUTION: This data input/data output control device and method wherein a plurality of write or read data configured of m=2 n +k bits (m, n, and k are integers) can be accessed during one clock cycle of an external clock signal. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

DE102007008180B4 Halbleiterspeicherelement, Speichersystem und Daten-Sende-/Empfangssystem 未知
公开(公告)号：DE102007008180B4
公开(公告)日：2018-12-20
申请号：DE102007008180
申请日：2007-02-12
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG HOE-JU , KIM KYU-HYOUN
IPC分类号： G11C29/52 , G06F11/08 , G06F11/10 , G11C7/10 , G11C29/42 , H03M13/29
摘要： Halbleiterspeicherelement, aufweisend:einen ersten Speicherzellenfeldblock (BLK1), der erste Daten (DO1) erzeugt;einen zweiten Speicherzellenfeldblock (BLK3), der zweite Daten (DO3) erzeugt;einen ersten Fehlererkennungscodegenerator (ECCG1), der einen ersten Fehlererkennungscode (1ec1) für die ersten Daten (DO1) erzeugt und der einen Anteil von Bits des ersten Fehlererkennungscodes (1ec1) mit einem Anteil von Bits eines zweiten Fehlererkennungscodes (2ec1) kombiniert, um ein erstes endgültiges Fehlererkennungssignal (fec1) zu erzeugen; undeinen zweiten Fehlererkennungscodegenerator (ECCG2), der den zweiten Fehlererkennungscode (2ec1) für die zweiten Daten (DO3) erzeugt und der verbleibende Bits des zweiten Fehlererkennungscodes (2ec1), die sich von dem Anteil von Bits des zweiten Fehlererkennungscodes (2ec1) unterscheiden, mit verbleibenden Bits des ersten Fehlererkennungscodes (1ec1), die sich von dem Anteil von Bits des ersten Fehlererkennungscodes (1ec1) unterscheiden, kombiniert, um ein zweites endgültiges Fehlererkennungssignal zu erzeugen.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式