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1. 发明专利

JP2006115489A Impedance adjustment circuit, integrated circuit including the same and impedance adjustment method of output driver using the same 有权
标题翻译：阻抗调整电路，包括相同的集成电路和使用其的输出驱动器的阻抗调整方法
公开(公告)号：JP2006115489A
公开(公告)日：2006-04-27
申请号：JP2005276474
申请日：2005-09-22
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , LEE JAE-JUN , KIM KYU-HYOUN
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H04L25/0278
摘要： PROBLEM TO BE SOLVED: To provide an impedance calibration circuit, integrated circuit including the same, and impedance adjustment method of an output driver utilizing the same. SOLUTION: The present invention relates to an impedance adjustment circuit including a calibration circuit, a first register and a second register. The calibration circuit generates a reference current by supplying an internal voltage to an external resistor connected to a calibration terminal and outputs first and second calibration signals in response to the reference current, first and second reference voltages and first and second impedance control signals. The first register increases/decreases a bit value of the first impedance control signal in response to the first calibration signal. The second register increases/decreases a bit value of the second impedance control signal in response to the second calibration signal. Thus, the skew of a signal transmitted by the output driver can be decreased. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种阻抗校准电路，包括该阻抗校准电路的集成电路和使用该阻抗校正电路的输出驱动器的阻抗调节方法。阻抗调整电路技术领域本发明涉及一种包括校准电路，第一寄存器和第二寄存器的阻抗调整电路。校准电路通过向连接到校准端子的外部电阻器提供内部电压来产生参考电流，并响应于参考电流，第一和第二参考电压以及第一和第二阻抗控制信号而输出第一和第二校准信号。第一寄存器响应于第一校准信号增加/减少第一阻抗控制信号的位值。第二寄存器响应于第二校准信号增加/减少第二阻抗控制信号的位值。因此，可以减少由输出驱动器发送的信号的偏斜。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2007220278A Semiconductor memory device and memory system including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：JP2007220278A
公开(公告)日：2007-08-30
申请号：JP2007029753
申请日：2007-02-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , KIM KYU-HYOUN
IPC分类号： G11C29/42
CPC分类号： H03M13/29 , G06F11/08 , G06F11/1008 , G11C7/1006 , G11C29/42 , G11C2029/0411 , G11C2207/104
摘要： PROBLEM TO BE SOLVED: To disclose a semiconductor memory device and a memory system including the same. SOLUTION: The semiconductor memory device is provided with a first memory cell array block for generating first data, a second memory cell array for generating second data, a first error detection code generator for generating a first error detection code for the first data, and generating a first final error detection signal by combining a portion of bits of the first error detection code with a portion of bits of a second error detection code, and a second error detection code generator for generating a second error detection code for the second data, and generating a second final error detection signal by combining remaining bits excluding the portion of bits of the second error detection code with remaining bits excluding the portion of bits of the first error detection code. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：公开半导体存储器件和包括该半导体存储器件的存储器系统。解决方案：半导体存储器件设置有用于产生第一数据的第一存储单元阵列块，用于产生第二数据的第二存储单元阵列，用于产生第一数据的第一错误检测码的第一错误检测码产生器并且通过将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合来产生第一最终错误检测信号，以及第二错误检测码发生器，用于生成第二错误检测码的第二错误检测码数据，并且通过将排除第二错误检测码的位的部分的剩余比特与除了第一错误检测码的比特的部分之外的剩余比特来生成第二最终错误检测信号。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007183959A Memory system having improved additive latency and control method 审中-公开
标题翻译：具有改进的添加剂延迟和控制方法的记忆系统
公开(公告)号：JP2007183959A
公开(公告)日：2007-07-19
申请号：JP2006355628
申请日：2006-12-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06 , G11C11/407 , G11C11/4076
CPC分类号： G06F13/1689
摘要： PROBLEM TO BE SOLVED: To provide a memory system capable of resetting the additive latency of a corresponding bank in every active motion, and to provide a control method. SOLUTION: The memory system comprises a memory element having a first bank and a second bank, and a memory controller having a lead request scheduling queue for storing read requests. When first and second read requests for the first bank and a third read request for the second bank are continuously generated, the memory controller applies first additive latency to the first and second read requests for the first bank and second additive latency to the third read request for the second bank to control the read request scheduling queue so that data is seamlessly output from the memory element. The additive latency is therefore smoothly controlled to control command queue design in a first-in first-out method. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够在每个主动运动中重置对应的组的附加等待时间的存储器系统，并提供控制方法。存储器系统包括具有第一存储体和第二存储体的存储元件，以及具有用于存储读取请求的引导请求调度队列的存储器控制器。当连续生成对第一组的第一和第二读取请求和第二组的第三读取请求时，存储器控制器对第一组的第一和第二读取请求应用第一附加等待时间，并且向第三读取请求对于第二存储体来控制读请求调度队列，使得数据从存储元件无缝地输出。因此，平滑地控制附加等待时间，以先入先出的方法来控制命令队列设计。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007151128A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007151128A
公开(公告)日：2007-06-14
申请号：JP2006320677
申请日：2006-11-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , JANG YOUNG-CHAN
IPC分类号： H03K19/0175 , G11C11/417
CPC分类号： G06F13/423 , G06F13/4072 , G11C7/1051 , G11C7/1057 , Y02D10/14 , Y02D10/151
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with variable power function. SOLUTION: In embodiment, the semiconductor device has at least one circuit element which is set to generate output data. At least one control circuit is set so as to variably control the power of the output data, based on the feedback from a receiving side semiconductor device which receives the output data. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有可变功率功能的半导体器件。解决方案：在实施例中，半导体器件具有被设置为产生输出数据的至少一个电路元件。至少一个控制电路被设置为基于从接收输出数据的接收侧半导体器件的反馈来可变地控制输出数据的功率。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2008165778A Memory device adopting dual clocking method for generating systematic code 有权
标题翻译：采用系统代码的双时钟方法的存储器件
公开(公告)号：JP2008165778A
公开(公告)日：2008-07-17
申请号：JP2007326573
申请日：2007-12-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU , KIM YOUN-CHEUL
IPC分类号： G06F12/16 , G11C29/42
CPC分类号： G06F11/1004
摘要： PROBLEM TO BE SOLVED: To provide a memory device adopting a dual clocking method for generating a systematic code.
SOLUTION: The memory device for generating a systematic code includes: a data patch unit for patching parallel data read from a memory core block in response to a first read pulse; a replica delay unit for generating a second read pulse delayed from the first read pulse by a period of time required for generating the CRC code corresponding to the read data; a CRC generating unit for generating the CRC code in response to the second read pulse delayed by a predetermined time after the first read pulse is generated; and a serializer for converting the parallel data to serial data in response to the first read pulse, and arrange the CRC code in an order for a number of bits of the serial data to generate a systematic code.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种采用双时钟方式生成系统代码的存储器件。用于生成系统代码的存储器件包括：数据补丁单元，用于响应于第一读取脉冲修补从存储器核心块读取的并行数据; 复制延迟单元，用于产生从所述第一读取脉冲延迟了生成对应于所读取的数据的CRC码所需的时间段的第二读取脉冲; CRC产生单元，用于响应于在产生第一读取脉冲之后延迟预定时间的第二读取脉冲来产生CRC码; 以及串行器，用于响应于第一读取脉冲将并行数据转换为串行数据，并且按照串行数据的位数的顺序排列CRC码以生成系统代码。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006229931A Multi-device system for forming daisy chain and its driving method 审中-公开
标题翻译：用于形成菊花链的多装置系统及其驱动方法
公开(公告)号：JP2006229931A
公开(公告)日：2006-08-31
申请号：JP2005376607
申请日：2005-12-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HOE-JU
IPC分类号： H04L12/28
CPC分类号： G11C5/04 , G11C29/02 , G11C29/50012
摘要： PROBLEM TO BE SOLVED: To provide a multi-device system capable of obtaining a delay time between a host device and a client device by a protocol using a constitution of a simplified circuit.
SOLUTION: The multi-device system comprises a chain bus and a daisy chain that oscillates by the host device and the client device. In accordance with the multi-device system and its driving method of the present invention, it is possible to grasp a data transmission delay time between the host device and the client device by measuring only an oscillation period of the daisy chain.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够通过使用简化电路的结构的协议在主机设备和客户端设备之间获得延迟时间的多设备系统。解决方案：多设备系统包括由主机设备和客户端设备振荡的链路总线和菊花链。根据本发明的多设备系统及其驱动方法，可以通过仅测量菊花链的振荡周期来掌握主机设备与客户端设备之间的数据传输延迟时间。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

DE102004044099B4 Streuspektrum-Taktgeber, Speichersystem und Taktsignalverzögerungsverfahren 未知
公开(公告)号：DE102004044099B4
公开(公告)日：2011-03-10
申请号：DE102004044099
申请日：2004-09-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN , CHUNG HOE-JU
IPC分类号： G06F1/04 , H03K3/02 , G11C7/22 , H03K3/013 , H03K5/156

8. 发明专利

ITMI20040834A1 SISTEMA DI MEMORIA MONTATO DIRETTAMENTE SU SCHEDA E PROCEDIMENTO ASSOCIATO 未知
公开(公告)号：ITMI20040834A1
公开(公告)日：2004-07-27
申请号：ITMI20040834
申请日：2004-04-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG HOE-JU , LEE JUNG-BAE
IPC分类号： G06F12/00 , G06F1/26 , G06F13/16

9. 发明专利

DE102005044083A1 Daisy chained multi-device system has several response bus units connecting host device input terminal to response output terminal of client device 未知
公开(公告)号：DE102005044083A1
公开(公告)日：2006-08-24
申请号：DE102005044083
申请日：2005-09-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG HOE-JU
IPC分类号： G06F13/40
摘要： A system drive bus (130) has several bus units connecting the host device output terminal to drive input terminal of the client device. A system response bus (140) has several response bus units connecting the host device input terminal to a response output terminal of the client device. A chain bus connects a drive input terminal of the N-th client device to response input terminal of the N-th client device. An independent claim is also included for method of operating multi-device system.

10. 发明专利

DE102004044099A1 Spread spectrum clock generator for use in memory system, has control circuit providing addresses of control codes to register circuit, which in turn provides control codes to delay circuit 未知
公开(公告)号：DE102004044099A1
公开(公告)日：2005-04-07
申请号：DE102004044099
申请日：2004-09-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN , CHUNG HOE-JU
IPC分类号： G06F1/04 , G11C7/22 , H03K3/013 , H03K3/02 , H03K5/156
摘要： The generator has a register circuit (54) to store control codes corresponding to a predetermined delay. A delay circuit (52) receives a control code having a predetermined number of bits. The delay circuit delays a fixed clock signal by a period of time determined by the control code. A control circuit (50) provides addresses of the codes to the register circuit, which in turn provides the control codes to the delay circuit. Independent claims are also included for the following: (A) a method of generating a spread spectrum clock (B) a memory system having a spread spectrum clock generator.

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