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1. 发明申请

WO2007072277A3 A CODER AND A METHOD OF CODING FOR CODES WITH A PARITY-COMPLEMENTARY WORD ASSIGNMENT HAVING A CONSTRAINT OF D=1, R=2 审中-公开
标题翻译：编码器和编码具有具有D = 1，R = 2的约束的符号补全字分配的编码的方法
公开(公告)号：WO2007072277A3
公开(公告)日：2007-10-18
申请号：PCT/IB2006054698
申请日：2006-12-08
申请人： KONINKL PHILIPS ELECTRONICS NV , SONY CORP , COENE WILLEM M J M , HEKSTRA ANDRIES P , YAMAGISHI HIROYUKI , NODA MAKOTA
发明人： COENE WILLEM M J M , HEKSTRA ANDRIES P , YAMAGISHI HIROYUKI , NODA MAKOTA
IPC分类号： H03M5/14 , G11B20/14
CPC分类号： G11B20/1426 , G11B20/10055 , G11B20/10296 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H03M7/40 , H03M13/29 , H03M13/31 , H03M13/3761 , H03M13/3972 , H03M13/41
摘要： Presently known d=l codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector. By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index T
摘要翻译：目前已知的d = l代码具有由连续的2T运行组成的长列车，并且出现最短的2T运行的总体高频率，这降低了位检测器的性能。通过使用MTR约束为2的代码，实现了位检测的改进。提出了一种以系统方式构建的代码，其提供MTR约束为2的代码。公开了这样的代码的变型，其中使用一个子代码，其中编码状态被分为编码类别以及代码字被分成代码字类型。然后，对于给定子码，如果所述下一子码的所述后续码字属于编码类的编码状态之一，则可以将类型t的码字与下一子码的码字连接，指数T

2. 发明专利

JP2012182623A Decoder, decoding method and program 有权
标题翻译：解码器，解码方法和程序
公开(公告)号：JP2012182623A
公开(公告)日：2012-09-20
申请号：JP2011043720
申请日：2011-03-01
申请人： Sony Corp , ソニー株式会社
发明人： YAMAGISHI HIROYUKI
IPC分类号： H03M13/19
CPC分类号： H03M13/3753 , H03M13/1102 , H03M13/1128 , H03M13/1137 , H03M13/114 , H03M13/134 , H03M13/2951 , H03M13/296 , H03M13/2975 , H03M13/35 , H03M13/37 , H03M13/3738 , H03M13/3746 , H04L1/0051 , H04L1/0061 , H04L1/0064 , H04L1/0625 , H04L1/0631
摘要： PROBLEM TO BE SOLVED: To reduce computation of iterative decoding.SOLUTION: A determination is made whether or not the decoding termination conditions are satisfied at an interval shorter than the single decode processing of iterative decoding, e.g. every time when check node operation and bit node operation for one group of bit nodes terminate in the group shuffled BP decoding. The remaining processing is continued when a determination is made that the decoding termination conditions are not satisfied at an interval shorter than the single decode processing, otherwise the remaining processing is not performed but the processing is terminated. The technology is applicable to a decoding circuit which decodes the LDPC codes.
摘要翻译：要解决的问题：减少迭代解码的计算。解决方案：确定解码终止条件是否以比迭代解码的单个解码处理更短的间隔来满足，例如，每次检查节点操作和一组比特节点的比特节点操作终止在组混洗BP解码中。当确定解码终止条件不是以比单个解码处理更短的间隔被满足时，继续进行剩余处理，否则不执行剩余处理，但处理终止。该技术适用于解码LDPC码的解码电路。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2010206570A Decoding apparatus and decoding method 审中-公开
标题翻译：解码设备和解码方法
公开(公告)号：JP2010206570A
公开(公告)日：2010-09-16
申请号：JP2009050200
申请日：2009-03-04
申请人： Sony Corp , ソニー株式会社
发明人： SHINAGAWA HITOSHI , NODA MAKOTO , YAMAGISHI HIROYUKI
IPC分类号： H03M13/41
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6561
摘要： PROBLEM TO BE SOLVED: To enable suppression of the size of memory which stores path selection information used in trace-back processes, and the latency accompanying decoding. SOLUTION: After xN-bit path selection information for radix -2 x is input with respect to a shift register 81 per clock and the amount corresponding to input k is stored, the amount of path selection information (kxN bits) is written at an address of a path memory RAM 82. In a trace-back circuit 83, the maximum likelihood path is selected, when a trace-back process takes place, based on the path selection information stored in the path memory RAM 82, and the value corresponding to each state on the maximum likelihood path is output as a decoding sequence. The present invention is applicable to receiving devices. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了能够抑制存储跟踪过程中使用的路径选择信息的存储器的大小以及伴随解码的等待时间。
解决方案：在每个时钟相对于移位寄存器81输入基数-2 x 的xN位路径选择信息之后，存储对应于输入k的量，路径选择量在路径存储器RAM82的地址处写入信息（kxN位）。在追溯回路83中，基于存储在路径存储器RAM 82中的路径选择信息，当追溯处理发生时，选择最大似然路径路径存储器RAM82，并且输出与最大似然路径上的每个状态相对应的值作为解码序列。本发明可应用于接收设备。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009171540A Transmission apparatus and method, reception device and method, and program 有权
标题翻译：传输装置和方法，接收装置和方法以及程序
公开(公告)号：JP2009171540A
公开(公告)日：2009-07-30
申请号：JP2008118548
申请日：2008-04-30
申请人： Sony Corp , ソニー株式会社
发明人： SHINAGAWA HITOSHI , NODA MAKOTO , YAMAGISHI HIROYUKI , KONDO KEITARO
IPC分类号： H04L1/00
CPC分类号： H04L1/0061 , H03M13/036 , H03M13/09 , H03M13/6516 , H04L1/0041
摘要： PROBLEM TO BE SOLVED: To select much more suitable generator polynomials, and to switch the selected plurality of generator polynomials according to data to be processed for use. SOLUTION: The maximum/minimum hamming distance (Max.d min ) being the maximum value of the minimum hamming distance (d min ) in each code length (n) of a code with code length (n) having k bit information words to which r bit parity is added about the information word is found, and code length n whose Max.d min is changed is found, and the n range (n min ≤n≤n max ) is found. In the n range, generator polynomials (G(x)) satisfying d min =Max.d min all the time are found out by full retrieval, and the generator polynomial in which the number of items (w) and the undetected error capability (P ud ) of the code is the minimum is selected from among the G(x) found out by full retrieval. The plurality of generator polynomials selected in this way are switched and used according to the type or code length of data to be processed. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：选择更合适的生成多项式，并根据待处理的数据来切换所选择的多个生成多项式。
解决方案：每个代码长度（n）中最大/最小汉明距离（Max.d min ）是最小汉明距离（d min ）的最大值找到具有相对于该信息字相加r位奇偶校验的k位信息字的代码长度（n）的代码，找到Max.d min 改变的代码长度n，并且发现n范围（n min ≤n≤n max ）。在n范围内，通过完全检索得到满足d min = Max.d min 的生成多项式（G（x）），生成多项式从完全检索发现的G（x）中选择代码的数量（w）和未检测到的错误能力（P ud ）的最小值。以这种方式选择的多个生成多项式根据要处理的数据的类型或代码长度进行切换和使用。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2006155878A Device and method for encoding, device and method for decoding, and recording medium 有权
标题翻译：用于编码的装置和方法，用于解码和记录介质的装置和方法
公开(公告)号：JP2006155878A
公开(公告)日：2006-06-15
申请号：JP2005369578
申请日：2005-12-22
申请人： Sony Corp , ソニー株式会社
发明人： NODA MAKOTO , YAMAGISHI HIROYUKI
IPC分类号： G11B20/14 , H03M7/14
摘要： PROBLEM TO BE SOLVED: To carry out encoding by using a code conversion table in which parities of code sequences are different until the time when code states become identical. SOLUTION: The code word allocation of the code conversion table is carried out such that the code word binding length of decoding time is 3 blocks and q 0 ≠q 1 is satisfied for an optional information sequence no matter which position of the first and second bits of an information word the insertion position of a DC control bit is inserted. For example, when information sequences d 0 and d 1 having temporary DC control bits 1 and 0 inserted into the head of an information sequence [1, 1, 0, 0, 0, 1, 0] are encoded by using a predetermined code conversion table with a state 3 set as a starting point, code states s 0 and s 1 become equal at s 0 =s 1 =6 at the third block, and the compliments q 0 and q 1 of 2 of totals of code sequences c 0 and c 1 until the time when the code states become equal are respectively 0 and 1, thereby establishing q 0 ≠q 1 . The invention is applicable to a recording/reproducing device or an encoding device. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过使用其中代码序列的奇偶校验不同直到代码状态变得相同的代码转换表来执行编码。解码：代码转换表的码字分配被执行，使得解码时间的码字绑定长度为3个块，并且q 0 ≠q 1 不管信息字的第一位和第二位的哪个位置，直流控制位的插入位置被插入，都满足可选的信息序列。例如，当具有插入到信息序列[1,1,10,0]的头部的临时DC控制位1和0的信息序列d 0 和d 1 0，1，0]通过使用设置为起始点的状态3的预定代码转换表进行编码，代码状态s 0 和s 1 在s 在第三块处的 0 = s 1 = 6，并且2的补码q 0 和q 1 代码序列总数c 0 和c 1 直到代码状态变为相等的时间分别为0和1，从而建立q 0 q 1 。本发明可应用于记录/再现设备或编码设备。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005045735A Code detecting apparatus and method, decoding apparatus and method, and information processing apparatus and method 审中-公开
标题翻译：代码检测装置和方法，解码装置和方法以及信息处理装置和方法
公开(公告)号：JP2005045735A
公开(公告)日：2005-02-17
申请号：JP2003280427
申请日：2003-07-25
申请人： Sony Corp , ソニー株式会社
发明人： YAMAGISHI HIROYUKI
IPC分类号： H03M13/19 , H03M13/09
摘要： PROBLEM TO BE SOLVED: To simplify the circuit configuration of a memory or the like for storing messages to be exchanged between nodes in the case of code detection using a computing element twice or more in one time of repeat processing. SOLUTION: A code detecting apparatus 1 includes a bit node processing arithmetic part 7 which calculates a message Q m, n to be dispatched from a bit node Y n to a check node X m , a check node processing arithmetic part 5 which calculates a message R m, n to be dispatched from the check node to the bit node, a memory 4 which stores Q m, n , and a memory 6 which stores an arithmetic result of the processing arithmetic part 5, and a check node processing computing element 5 temporarily finds A m , B m from the successively inputted messages Q m, n , is successively inputted with the message Q m, n again, successively calculates the message R m, n from this message and the calculated A m , B m and outputs the calculated message to the bit node processing arithmetic part 7. In such a case, (m) is unitariness of a set M(n). COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了简化存储器等的电路配置，用于在重复处理的一次中使用计算元件两次或更多次来存储在代码检测的情况下在节点之间交换的消息。解决方案：代码检测装置1包括：位节点处理算术部分7，其计算要从比特节点Y n 发送的消息Q m，n 到检查节点X m ，校验节点处理算术部分5，其计算要从校验节点发送到比特节点的消息R SB，m N n，存储器4 存储Q＆lt; SB＆gt; m，n＆lt; / SB＆gt;和存储处理运算部5的运算结果的存储器6，并且校验节点处理计算单元5临时找到A m 来自连续输入的消息Q m，n 的B m 再次与消息Q m，n 相继输入，连续计算消息R m，n 和计算出的A m ，B m ，并将计算出的消息输出到位节点处理算术部分7.在这种情况，（m）是集合M（n）的单位性。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2004289520A Encoding device and encoding method, recording medium and program 有权
公开(公告)号：JP2004289520A
公开(公告)日：2004-10-14
申请号：JP2003079556
申请日：2003-03-24
申请人： Sony Corp , ソニー株式会社
发明人： NODA MAKOTO , YAMAGISHI HIROYUKI
IPC分类号： G11B20/14 , H03M5/14 , H03M7/14
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1457
摘要： PROBLEM TO BE SOLVED: To perform encoding by using a code conversion table such that the parities of code sequences are up to the time point where the codes became identical are different. SOLUTION: According to the codeword allocation in the code conversion table, the constraint length of the codeword at the time of decoding is three blocks and a relation q 0 ≠q 1 is satisfied for an arbitrary information sequence by inserting a DC control bit in any of the first bit and the second bit of an information word. For example, an information sequence d 0 and an information sequence d 1 which are formed by respectively inserting temporary DC control bits 1 and 0 at the head of an information sequence [1,1,0,0,0,1,0] are encoded by using a predetermined code conversion table. In this case, an encoding state s 0 and an encoding state s 1 , when the state 3 is the start point, become identical at the third block: s 0 =s 1 =6. Since two's complement q 0 of the total of a code sequence c 0 until the codes become identical is 0 and two's complement q 1 of the total of the code sequence c 1 is 1, the relation q 0 ≠q 1 is satisfied. The method can be applied to a recording and reproducing device or an encoding device. COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2010056660A Encoding apparatus and method 有权
标题翻译：编码装置和方法
公开(公告)号：JP2010056660A
公开(公告)日：2010-03-11
申请号：JP2008217004
申请日：2008-08-26
申请人： Sony Corp , ソニー株式会社
发明人： YAMAGISHI HIROYUKI
IPC分类号： H03M13/19 , G06F11/10
CPC分类号： H03M13/15 , H03M13/116 , H03M13/6561
摘要： PROBLEM TO BE SOLVED: To make processing concerning encoding attain a high speed.
SOLUTION: A combination circuit 253 obtains coefficients of q
j (x
2p ) one by one from higher rank 2p symbols of a (NK) step register 251, subtracts multiplied values of these coefficients of 2p piece and generator polynomials from values composed of register output and information symbols of new 2p pieces, then, uses them as input values to the next register. Since the coefficients of q
j (x
2p ) for the 2p symbols obtained from the register, are simultaneously obtained, multiplication of the coefficients and the generator polynomials can be simultaneously performed. The invention can apply to a circuit creating a parity in an be applied to the encoding apparatus.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使得关于编码的处理达到高速。解决方案：组合电路253从（NK）步进寄存器251的较高级2p个符号逐个地获得q j （x 2p ）的系数，减去从2p的寄存器输出和信息符号组成的值乘以2p段和生成多项式的这些系数的乘积值，然后将它们作为下一个寄存器的输入值。由于从寄存器获得的2p符号的q j （x 2p ）的系数被同时获得，所以可以同时执行系数和生成多项式的乘法。本发明可以应用于在编码装置中应用奇偶校验的电路。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008278184A Decoding apparatus 有权
标题翻译：解码设备
公开(公告)号：JP2008278184A
公开(公告)日：2008-11-13
申请号：JP2007119090
申请日：2007-04-27
申请人： Sony Corp , ソニー株式会社
发明人： SHINAGAWA HITOSHI , YAMAGISHI HIROYUKI , NODA MAKOTO
IPC分类号： H03M13/19
CPC分类号： H03M13/1137 , H03M13/1111 , H03M13/6566
摘要： PROBLEM TO BE SOLVED: To execute decoding processing of LDPC (low density parity check) code at high speed with a simple configuration. SOLUTION: A storage section determining part 201 controls processing for determining a storage section of logarithmic likelihood ratios λ n or logarithmic posteriori probability radios q n in each of respective RAMs of this decoding apparatus. The storage section determined by the storage section determining part 201 is supplied to a control part 203 and stored in a memory, or the like in a controller. A decoding part 202 reads the logarithmic likelihood ratios λ n , or logarithmic posteriori probability radios q n in each of respective RAMs of this decoding apparatus, on the basis of the storage section determined by the storage section determining part 201 and controls processing for coding a received codeword. This invention is applicable to a decoding apparatus for decoding the LDPC code. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：以简单的配置高速执行LDPC（低密度奇偶校验）码的解码处理。解决方案：存储部分确定部分201控制用于确定每个相应RAM中的对数似然比λ n 或对数后验概率无线电q n 的存储部分的处理的解码装置。由存储部确定部分201确定的存储部分被提供给控制部分203并存储在控制器中的存储器等中。解码部分202基于存储部分读取该解码装置的每个RAM中的对数似然比λSB> n 或对数后验概率无线电q n 由存储部分确定部分201确定并且控制用于编码所接收的码字的处理。本发明可应用于解码LDPC码的解码装置。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2013200366A Camera module and camera device 审中-公开
标题翻译：相机模块和相机设备
公开(公告)号：JP2013200366A
公开(公告)日：2013-10-03
申请号：JP2012067290
申请日：2012-03-23
申请人： Sony Corp , ソニー株式会社
发明人： FURUSAWA TOSHIHIRO , HIGASHITSUTSUMI YOSHIHITO , KABAYA YOSHITERU , KINUGASA YUKIHISA , KAWABE HIDEO , ISHIDA TAKEHISA , KATO YUSAKU , NAGAI NOBUYUKI , MORITA MASAYOSHI , YAMAGISHI HIROYUKI
IPC分类号： G02B7/28 , G02B7/04 , G03B3/04 , G03B13/32 , H04N5/225 , H04N5/232 , H04N5/335
CPC分类号： H04N5/2257 , G02B7/08 , G03B3/04 , G03B2205/0053 , H04N5/2253 , H04N5/2254 , H04N5/23212
摘要： PROBLEM TO BE SOLVED: To provide a camera module and a camera which enable movement of an image sensor and also enable large lenses with large-aperture lenses, zooming or the like to be mounted.SOLUTION: An actuator unit comprises: a movable joint part to which one end of an imaging element is secured and which is movable in response to back-and-forth movement; a parallel link mechanism part, one end of which is mounted on the movable joint part while the other end of which is secured, and which holds the imaging element at a target position synchronized with movement of the movable joint part; and a needle, one end of which is joined so as to allow transmission of displacement motion in relation to a joined area between the movable joint part and the one end of the parallel link mechanism part, and which is displaced by a displacement corresponding to a level of applied driving voltage, to cause the imaging element to move back and forth between a first position and a second position in the optical axis direction.
摘要翻译：要解决的问题：提供一种能够使图像传感器移动的相机模块和照相机，并且还能够安装具有大孔径透镜，变焦等的大型透镜。解决方案：致动器单元包括：可动接头部分成像元件的一端被固定到其上并可响应往复运动而移动; 平行连杆机构部分，其一端安装在可动接头部分上，同时其另一端固定，并将成像元件保持在与可动接头部分的运动同步的目标位置; 以及针，其一端被接合以便允许相对于可动接头部分和平行连杆机构部分的一端之间的接合区域的位移运动的传递，并且被移位相当于施加的驱动电压的电平，使得成像元件在光轴方向上的第一位置和第二位置之间来回移动。

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