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    • 1. 发明授权
    • Method and apparatus for maintaining an order of write operations by
processors in a multiprocessor computer to maintain memory consistency
    • 用于维护多处理器计算机中的处理器的写入操作顺序以维持存储器一致性的方法和装置
    • US5900020A
    • 1999-05-04
    • US678372
    • 1996-06-27
    • Robert J. SafranekThomas D. LovettRobert T. JoerszBruce M. Gilbert
    • Robert J. SafranekThomas D. LovettRobert T. JoerszBruce M. Gilbert
    • G06F12/08G06F13/14G06F13/24G06F13/42
    • G06F12/0828G06F12/0813G06F2212/2542
    • A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.
    • 公开了一种在诸如多节点计算机系统的多处理器计算机中维持处理器一致性的方法和装置。 处理器在其先前的写入操作完成之前进行写入操作,同时保持处理器的一致性。 写入操作从处理器的请求开始,使存储在其他节点中的数据的副本无效。 该当前无效请求被排队,同时向处理器确认请求完成,即使它尚未实际完成。 处理器继续通过更改数据来完成写入操作。 然后,它可以执行后续操作,包括其他写入操作。 然而,排队的请求不会传输到计算机中的其他节点,直到处理器的所有先前的无效请求都完成为止。 这确保当前的无效请求不会通过先前的无效请求。 无效请求在处理器未完成的无效列表出现并被完成时被添加和删除。 通过通知与当前无效请求相关的链接列表中的节点,节点共享的数据现在无效,则完成无效请求。
    • 2. 发明授权
    • Maintaining order of write operations in a multiprocessor for memory consistency
    • 维护多处理器中写入操作的顺序,以保持内存一致性
    • US06493809B1
    • 2002-12-10
    • US09493782
    • 2000-01-28
    • Robert J. SafranekThomas D. Lovett
    • Robert J. SafranekThomas D. Lovett
    • G06F1300
    • G06F13/4243
    • A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The method is useful in multiprocessor systems such as a distributed shared memory (DSM) or non-uniform memory access (NUMA) machines that include a number of interconnected processor nodes each having local memory and caches that store copies of the same data. In such a multiprocessor system using the Scalable Content Interface (SCI) protocol, an invalidate request is sent from the head node on the sharing list to a succeeding node on the list. In response to the invalidate request, the succeeding node issues an invalidate acknowledgement before the cache line is actually invalidated. After issuing the invalidate acknowledgement, the succeeding node initiates invalidation of the cache line. The invalidate acknowledgement can take the form of a response to the head node or a forwarding of the invalidate request to the next succeeding node on the list. To maintain processor consistency, a flag is set each time an invalidate acknowledgement is sent. The flag is cleared after the invalidation of the cache line is completed. Cacheable transactions received at the succeeding node while a flag is set are delayed until the flag is cleared.
    • 一种使共享高速缓存行无效化的方法,例如在共享列表上通过在实际使高速缓存行无效之前发出无效确认。 该方法在诸如分布式共享存储器(DSM)或非均匀存储器访问(NUMA)机器的多处理器系统中是有用的,其包括多个互连的处理器节点,每个互连处理器节点具有存储相同数据的副本的本地存储器和高速缓存。 在使用可伸缩内容接口(SCI)协议的这种多处理器系统中,将无效请求从共享列表上的头节点发送到列表上的后续节点。 响应于无效请求,后续节点在高速缓存行实际无效之前发出无效确认。 发出无效确认后,后续节点启动高速缓存行的无效。 无效确认可以采取对头节点的响应的形式或将无效请求转发到列表上的下一个后续节点。 为了保持处理器的一致性,每次发送无效确认时都会设置一个标志。 标志在高速缓存行无效完成后被清除。 在设置标志时在后续节点处接收的可缓存事务被延迟直到该标志被清除。
    • 7. 发明授权
    • Method and system for communicating interrupts between nodes of a multinode computer system
    • 用于在多节点计算机系统的节点之间通过网络通信中断的方法和系统
    • US06247091B1
    • 2001-06-12
    • US08848545
    • 1997-04-28
    • Thomas D. Lovett
    • Thomas D. Lovett
    • G06F1324
    • G06F13/24
    • Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among the interrupt controller, the state machine, and the queues is coordinated by a queue manager. For sending an interrupt, the interrupt controller accepts an interrupt placed on a bus within the node and intended for another node and stores it in the send queue. The controller then notifies the interrupt source that the interrupt has been accepted before it is transmitted to other node. The interrupt has a first form suitable for transmission on the bus. A state machine within the node takes the interrupt from the send queue and puts the interrupt into a second form suitable for transmission across a network connecting the multiple nodes. For receiving an interrupt, the state machine accepts an interrupt from another node and stores it in the receive queue, notifying the interrupt source that the interrupt has been accepted before its is placed on the node bus. The interrupt has the second form suitable for transmission across the network. The interrupt controller takes the interrupt from the receive queue and puts it in the first form suitable for transmission on the bus.
    • 多节点计算机系统的每个节点包括中断控制器,一对发送和接收队列,以及用于在节点之间通信中断的状态机。 中断控制器,状态机和队列之间的通信由队列管理器进行协调。 为了发送中断,中断控制器接受放置在节点内的总线上的中断,并且用于另一个节点并将其存储在发送队列中。 然后,控制器通知中断源,在中断被发送到其他节点之前已被接受。 中断具有适合在总线上传输的第一种形式。 节点内的状态机从发送队列中获取中断,并将中断置于适合通过连接多个节点的网络进行传输的第二种形式。 为了接收中断,状态机接受来自另一个节点的中断,并将其存储在接收队列中,通知中断源在中断被放置在节点总线之前被接受。 中断具有适合于跨网络传输的第二种形式。 中断控制器从接收队列中取出中断,并将其置于适合在总线上传输的第一种形式。
    • 8. 发明授权
    • Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system
    • 使用全局监听在单一相干系统中为分布式计算机节点提供高速缓存一致性的方法和装置
    • US06973544B2
    • 2005-12-06
    • US10045927
    • 2002-01-09
    • Thomas B. BergBruce M. GilbertThomas D. Lovett
    • Thomas B. BergBruce M. GilbertThomas D. Lovett
    • G06F12/00G06F12/08G06F13/00
    • G06F12/0813G06F12/0817
    • A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line. The disclosure provides support for a third level remote cache for each node.
    • 一种用于在多处理器系统中提供高速缓存一致性的方法和装置,其被配置为具有每个节点本地的存储器的两个或更多个节点以及互连所有节点的标签和地址交叉开关系统以及数据交叉开关系统。 本公开适用于利用分布在多于一个节点上的系统存储器并且利用利用该节点本地的存储器的每个节点中的数据状态的窥探的多处理器计算机系统。 全局侦听用于提供数据标签的单一序列化。 中央交叉开关控制器同时检查所有节点的给定地址线的高速缓存状态标签,并向请求数据的节点发出适当的回复,同时向系统中的任何其他节点生成其他数据请求,以便保持高速缓存的一致性并提供 请求的数据。 该系统通过将这样的存储器划分为对于任何给定的高速缓存行互斥的本地和远程类别来利用每个节点本地的存储器。 本公开提供了对于每个节点的第三级远程高速缓存的支持。