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1. 发明申请

US20060253806A1 CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS 有权
标题翻译：基于内容的VLSI设计预测
公开(公告)号：US20060253806A1
公开(公告)日：2006-11-09
申请号：US10908342
申请日：2005-05-09
申请人： Robert Allen , Daria Dooling , Jason Hibbeler , Daniel Maynard , Sarah Prue , Ralph Williams
发明人： Robert Allen , Daria Dooling , Jason Hibbeler , Daniel Maynard , Sarah Prue , Ralph Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system, method and program product for predicting yield of a VLSI design. A method is providing including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
摘要翻译：一种用于预测VLSI设计产量的系统，方法和程序产品。一种提供方法包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

2. 发明申请

US20070240090A1 YIELD OPTIMIZATION IN ROUTER FOR SYSTEMATIC DEFECTS 失效
标题翻译：系统缺陷路由器的优化优化
公开(公告)号：US20070240090A1
公开(公告)日：2007-10-11
申请号：US11279262
申请日：2006-04-11
申请人： Jeanne Bickford , Markus Buehler , Jason Hibbeler , Juergen Koehl , Daniel Maynard
发明人： Jeanne Bickford , Markus Buehler , Jason Hibbeler , Juergen Koehl , Daniel Maynard
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5077
摘要： Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.
摘要翻译：本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。针对具有不同宽度的电线建立了不同的结构标识符。此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。

3. 发明申请

US20070245283A1 MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CONSTRAINTS FOR HIERARCHICAL DESIGNS 失效
标题翻译：用于分层设计的网格约束的最小布局基于假设的艺术品法规
公开(公告)号：US20070245283A1
公开(公告)日：2007-10-18
申请号：US11279758
申请日：2006-04-14
申请人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
发明人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译：一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置使用线性规划解决方案的结果的至少一个小区。

4. 发明申请

US20060101356A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101356A1
公开(公告)日：2006-05-11
申请号：US10904225
申请日：2004-10-29
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

5. 发明申请

US20050050500A1 THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS 失效
公开(公告)号：US20050050500A1
公开(公告)日：2005-03-03
申请号：US10604962
申请日：2003-08-28
申请人： Robert Allen , Jason Hibbeler , Gustavo Tellez
发明人： Robert Allen , Jason Hibbeler , Gustavo Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

6. 发明申请

US20050050501A1 THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS 审中-公开
公开(公告)号：US20050050501A1
公开(公告)日：2005-03-03
申请号：US10604963
申请日：2003-08-28
申请人： Robert Allen , Jason Hibbeler , Gustavo Tellez
发明人： Robert Allen , Jason Hibbeler , Gustavo Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

7. 发明申请

US20070198961A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070198961A1
公开(公告)日：2007-08-23
申请号：US11697798
申请日：2007-04-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

8. 发明申请

US20060150130A1 INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS 有权
标题翻译：使用VORONOI DIAGRAMS的集成电路增益
公开(公告)号：US20060150130A1
公开(公告)日：2006-07-06
申请号：US10709292
申请日：2004-04-27
申请人： Robert Allen , Michael Gray , Jason Hibbeler , Mervyn Tan , Robert Walker
发明人： Robert Allen , Michael Gray , Jason Hibbeler , Mervyn Tan , Robert Walker
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.
摘要翻译：一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。

9. 发明申请

US20070277129A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070277129A1
公开(公告)日：2007-11-29
申请号：US11837732
申请日：2007-08-13
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

10. 发明申请

US20060101357A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101357A1
公开(公告)日：2006-05-11
申请号：US10905008
申请日：2004-12-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

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