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    • 5. 发明授权
    • Multilevel imprint lithography
    • 多层压印光刻
    • US07256435B1
    • 2007-08-14
    • US10453329
    • 2003-06-02
    • Pavel KornilovichYong ChenDuncan StewartR. Stanley WilliamsPhilip J. KuekesMehmet Fatih Yanik
    • Pavel KornilovichYong ChenDuncan StewartR. Stanley WilliamsPhilip J. KuekesMehmet Fatih Yanik
    • H01L27/10
    • H01L21/76838B81C99/009B81C2201/0153B82Y10/00B82Y40/00G03F7/0002
    • A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.
    • 提供具有突出图案的模具,其通过压印过程被压入薄聚合物膜。 提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。 打印印记被配置成形成大致平行的纳米线的阵列,其具有(1)X方向上的微尺寸,(2)在Y方向上的纳米尺寸和纳米间距,以及Z方向上的三个或更多个不同的高度。 如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。 模具中的突出图案在薄聚合物膜中产生凹陷,因此聚合物层获得模具上图案的相反。 在除去模具之后,处理膜,使得聚合物图案可以在基底上的金属/半导体图案上转印。
    • 10. 发明授权
    • Configurable nanoscale crossbar electronic circuits made by electrochemical reaction
    • 通过电化学反应制造的可配置的纳米级横梁电子电路
    • US06891744B2
    • 2005-05-10
    • US10289703
    • 2002-11-06
    • Yong ChenR. Stanley Williams
    • Yong ChenR. Stanley Williams
    • G11C13/02G11C13/00H01L21/31H01L21/44
    • G11C13/0009B82Y10/00G11C13/025G11C2213/34G11C2213/77G11C2213/81Y10S438/957Y10S977/936
    • Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material. The method comprises: (a) forming the first layer on a substrate; (b) forming a solid phase of a configurable material on the first layer at least in areas where the second layer is to cross the first layer; (c) forming the second layer on the configurable material, over the first layer; and (d) changing a property of the configurable material to thereby configure the nanoscale devices.
    • 可配置电子电路包括由第二层金属/半导体纳米级线交叉的一层金属/半导体纳米级线的交叉点阵列,其中线之间具有可配置层。 提供了通过使用固体材料作为可配置层的氧化或还原方法来改变可配置层的厚度和/或电阻的方法。 具体地,提供一种用于在可配置设备的交叉开关阵列中配置纳米级器件的方法,其包括第一纳米级线层的交点的阵列,其包括第一金属或第一半导体材料,所述第一金属或第一半导体材料由第二纳米级线交叉,所述第二金属或第二半导体材料包括第二金属 或第二半导体材料。 该方法包括:(a)在衬底上形成第一层; (b)至少在所述第二层与所述第一层交叉的区域中,在所述第一层上形成可配置材料的固相; (c)在所述可配置材料上形成在所述第一层上的所述第二层; 和(d)改变可配置材料的特性,从而配置纳米级器件。