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1. 发明申请

WO2016048651A1 DEPENDENCY-PREDICTION OF INSTRUCTIONS 审中-公开
标题翻译：指示的依赖性预测
公开(公告)号：WO2016048651A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/048959
申请日：2015-09-08
申请人： QUALCOMM INCORPORATED
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , BROWN, Melinda
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30149 , G06F9/38 , G06F9/3836 , G06F9/3842 , G06F9/3885
摘要： Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.
摘要翻译：用于依赖性预测的系统和方法包括在处理器的指令流水线中执行指令，并且检测诸如If-Then（IT）指令之类的有条件的控制指令，该指令将依赖行为强加于一个或多个依赖说明。在执行第一指令之前，基于条件块大小和指令流水线的一个或多个参数，进行依赖性预测以确定第一指令是否是条件施加控制指令的依赖指令。基于依赖关系预测执行第一指令。当第一条指令是依赖性错误预测时，减轻相关的依赖关系错误估计。如果第一指令是分支指令，则缓解涉及训练分支预测跟踪机制以正确依赖 - 预测第一指令的将来出现。

2. 发明申请

WO2013109696A2 DETERMINING CACHE HIT/MISS OF ALIASED ADDRESSES IN VIRTUALLY-TAGGED CACHE(S), AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：确定VARTUALLY-TAGGED CACHE（S）中的缓存地址的高速缓存/错误，以及相关系统和方法
公开(公告)号：WO2013109696A2
公开(公告)日：2013-07-25
申请号：PCT/US2013/021849
申请日：2013-01-17
申请人： QUALCOMM INCORPORATED
发明人： DIEFFENDERFER, James Norris , CLANCY, Robert D , SPEIER, Thomas Philip
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1045
摘要： Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually-tagged cache(s) are disclosed. In one embodiment, a virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses, respectively. The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner, the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses, even in the presence of aliased addressing.
摘要翻译：公开了用于确定虚拟标记的高速缓存中的别名地址的高速缓存命中/未命中的装置和相关系统和方法。在一个实施例中，提供了用于VIVT高速缓存的虚拟混叠高速缓存命中/未命中检测器。检测器包括TLB，其被配置为基于第一虚拟地址从VIVT高速缓存中接收第一虚拟地址和第二虚拟地址，该第一虚拟地址和第二虚拟地址是从索引读入到VIVT高速缓存中产生的。 TLB还被配置为分别生成从第一和第二虚拟地址转换的第一和第二物理地址。检测器还包括比较器，其被配置为接收第一物理地址和第二物理地址，并且基于第一和第二物理地址的比较来实现别名高速缓存命中/未命中指示符的生成。以这种方式，即使在存在别名寻址的情况下，虚拟混叠高速缓存命中/未命中检测器也正确地产生高速缓存命中和高速缓存未命中。

3. 发明申请

WO2013109679A1 METHOD FOR FILTERING TRAFFIC TO A PHYSICALLY-TAGGED DATA CACHE 审中-公开
标题翻译：将流量过滤到物理标签数据缓存的方法
公开(公告)号：WO2013109679A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/021822
申请日：2013-01-17
申请人： QUALCOMM INCORPORATED
发明人： CLANCY, Robert D , DIEFFENDERFER, James Norris , SPEIER, Thomas Philip
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0864 , G06F12/1045 , G06F12/1063 , Y02D10/13
摘要： Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
摘要翻译：公开了数据高速缓存的实施例，其提供了对数据高速缓存的物理标记的标签阵列的访问的数量的大量减少。通常，数据高速缓存包括存储数据元素，物理标记的标签阵列和虚拟标记的标签阵列的数据阵列。在一个实施例中，虚拟标记的标签阵列接收虚拟地址。如果虚拟标记的标签阵列中的虚拟地址匹配，则虚拟标记的标签阵列将数据阵列中的虚拟地址标记在虚拟标记的数组中。此外，在一个实施例中，虚拟标记的标签阵列禁用物理标记的标签阵列。使用由虚拟标记的标签数组输出的方式，寻址数据数组中所需的数据元素。

4. 发明申请

WO2009046326A1 LINK STACK REPAIR OF ERRONEOUS SPECULATIVE UPDATE 审中-公开
标题翻译：链路堆栈修复错误的参数更新
公开(公告)号：WO2009046326A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078789
申请日：2008-10-03
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
发明人： DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发出链路堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

5. 发明申请

WO2008095025A1 APPARATUS AND METHODS TO REDUCE CASTOUTS IN A MULTI-LEVEL CACHE HIERARCHY 审中-公开
标题翻译：减少多层次高速缓存中的突发事件的方法和方法
公开(公告)号：WO2008095025A1
公开(公告)日：2008-08-07
申请号：PCT/US2008/052507
申请日：2008-01-30
申请人： QUALCOMM INCORPORATED , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. When it is determined that displaced lines have already been allocated in a higher level, the allocations of the displaced cache lines are prevented in the next level cache, thus, reducing castouts. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译：技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。当确定已移位的行已经被分配在较高级别时，在下一级高速缓存中防止移位的高速缓存行的分配，从而减少转移。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。防止所选线路的分配节省与分配相关联的功率。

6. 发明申请

WO2008092045A1 SEGMENTED PIPELINE FLUSHING FOR MISPREDICTED BRANCHES 审中-公开
标题翻译：用于错误分支的SEGMENTED管道冲洗
公开(公告)号：WO2008092045A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/051966
申请日：2008-01-24
申请人： QUALCOMM Incorporated , MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
发明人： MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： A processor pipeline is segmented into an upper portion - prior to instructions going out of program order - and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
摘要翻译：处理器管线被分割成上部，在指令超出程序顺序之前，以及超出上部的一个或多个下部。在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。较低的管道可以继续执行，直到错误的分支指令确认，此时所有未提交的指令都从较低的管道冲洗。可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

7. 发明申请

WO2008092044A2 CONTENT-TERMINATED DMA 审中-公开
标题翻译：内消旋DMA
公开(公告)号：WO2008092044A2
公开(公告)日：2008-07-31
申请号：PCT/US2008/051965
申请日：2008-01-24
申请人： QUALCOMM Incorporated , SAPP, Kevin Allen , DIEFFENDERFER, James Norris
发明人： SAPP, Kevin Allen , DIEFFENDERFER, James Norris
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： A Content-Terminated Direct Memory Access (CT-DMA) circuit autonomously transfers data of an unknown length from a source to a destination, terminating the transfer based on the content of the data. Filter criteria are provided to the CT-DMA prior to the data transfer. The filter criteria include pattern data that are compared to transfer data, and transfer termination rules for interpreting the comparison results. Data are written to the destination until the filter criteria are met. Representative filter criteria may include that one or more units of transfer data match pattern data; that one or more units of transfer data fail to match pattern data; or that one or more units of transfer data match pattern data a predetermined number of times.
摘要翻译：内容终止的直接存储器访问（CT-DMA）电路自主地将来自源的未知长度的数据传送到目的地，基于数据的内容终止传送。在数据传输之前，将过滤标准提供给CT-DMA。过滤标准包括与传输数据进行比较的模式数据，以及用于解释比较结果的转移终止规则。将数据写入目的地，直到满足过滤条件。代表性的过滤标准可以包括一个或多个传送数据单元匹配模式数据; 一个或多个传输数据单元不能匹配模式数据; 或者一个或多个传送数据单元与图案数据匹配预定次数。

8. 发明申请

WO2008073741A1 METHODS AND APPARATUS FOR LOW-COMPLEXITY INSTRUCTION PREFETCH SYSTEM 审中-公开
标题翻译：低复杂度指导预制系统的方法和装置
公开(公告)号：WO2008073741A1
公开(公告)日：2008-06-19
申请号：PCT/US2007/086254
申请日：2007-12-03
申请人： QUALCOMM Incorporated , MORROW, Michael William , DIEFFENDERFER, James Norris
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0862
摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X% into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
摘要翻译：当在指令高速缓存中发生错误时，使用预取技术来最小化错误率，存储器访问带宽和功率使用。当缺失发生时，预取技术之一运行。接收到在指令高速缓存中丢失的获取地址的通知。分析导致遗漏的提取地址，以确定提取地址的属性，并根据属性预取一行指令。该属性可以指示提取地址是非顺序操作的目标地址。另一个属性可以指示提取地址是非顺序操作的目标地址，并且目标地址大于高速缓存行中的X％。进一步的属性可以指示提取地址是指令高速缓存中的偶数地址。可以组合这些属性以确定是否预取。

9. 发明申请

WO2006091857A1 METHODS AND APPARATUS TO INSURE CORRECT PREDECODE 审中-公开
标题翻译：确保正确预测的方法和装置
公开(公告)号：WO2006091857A1
公开(公告)日：2006-08-31
申请号：PCT/US2006/006677
申请日：2006-02-24
申请人： QUALCOMM INCORPORATED , SMITH, Rodney, Wayne , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney, Wayne , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/30 , G06F9/45
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX -1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译：公开了用于确保指令串的同步预解码的技术。指令串包含来自可变长度指令集和嵌入数据的指令。一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。该技术还包括当程序被编译或组合到指令串中并且将长度为MAX -1的填充插入指令串中以确定嵌入数据段的结束时，到嵌入数据的结尾。在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

10. 发明申请

WO2017146860A1 COMBINING LOADS OR STORES IN COMPUTER PROCESSING 审中-公开
标题翻译：计算机处理中的负载或存储组合
公开(公告)号：WO2017146860A1
公开(公告)日：2017-08-31
申请号：PCT/US2017/015117
申请日：2017-01-26
申请人： QUALCOMM INCORPORATED
发明人： JAGET, Kevin , MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/30 , G06F9/38 , G06F9/345
CPC分类号： G06F9/3017 , G06F9/30021 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/3832
摘要： Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.
摘要翻译：这里公开的各方面涉及组合指令以在处理器中处理指令时从存储器中加载数据或将数据存储在存储器中。一种示例性方法包括：检测流水线指令的模式，以使用可用总线宽度的第一部分访问存储器，并且响应于检测到模式，将流水线指令组合成单条指令以使用可用总线的第二部分访问存储器宽度比第一部分宽。包括使用所公开的方面的处理器的设备可以以更有效的方式执行当前可用的软件，而不修改软件。

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