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1. 发明公开

EP3387541A1 SINGLE-LINE PMIC-HOST LOW-LEVEL CONTROL INTERFACE 审中-公开
公开(公告)号：EP3387541A1
公开(公告)日：2018-10-17
申请号：EP16801917.2
申请日：2016-11-10
申请人： Qualcomm Incorporated
发明人： MISHRA, Lalan , CHUN, Christopher Kong Yee , TAN, Chiew-Guan , LEE, Gordon , SUTTON, Todd
IPC分类号： G06F13/42
CPC分类号： H04L47/12 , G06F13/4278 , G06F13/4295 , H04L5/14 , H04L49/109 , H04W28/0221 , H04W52/0229 , Y02D70/122 , Y02D70/26
摘要： System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

2. 发明申请

WO2022081321A1 STATIC AND INTERMITTENT DYNAMIC MULTI-BIAS CORE FOR DUAL PAD VOLTAGE LEVEL SHIFTER 审中-公开
公开(公告)号：WO2022081321A1
公开(公告)日：2022-04-21
申请号：PCT/US2021/051697
申请日：2021-09-23
申请人： QUALCOMM INCORPORATED
发明人： PRESSWALA, Aliasgar , CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K3/356
摘要： An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

3. 发明申请

WO2015160452A2 HIGH-VOLTAGE INPUT RECEIVER USING LOW-VOLTAGE DEVICES 审中-公开
标题翻译：使用低电压设备的高压输入接收器
公开(公告)号：WO2015160452A2
公开(公告)日：2015-10-22
申请号：PCT/US2015/019958
申请日：2015-03-11
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K5/24
CPC分类号： H03K5/08 , H03K5/24 , H03K19/00315
摘要： An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.
摘要翻译：用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。降压装置将高电压域组合信号转换成降压低电压域信号。

5. 发明公开

EP2904638A1 ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS 有权
标题翻译： ELEKTROSTATISCHER SCHUTZFÜRGESTAPELTE INTEGRIERTE SCHALTUNGEN MIT MEHREREN CHIPS
公开(公告)号：EP2904638A1
公开(公告)日：2015-08-12
申请号：EP13779997.9
申请日：2013-10-03
申请人： Qualcomm Incorporated
发明人： HENDERSON, Brian M. , TAN, Chiew-Guan , UVIEGHARA, Gregory A. , JALILIZEINALI, Reza
IPC分类号： H01L23/60 , H01L23/525 , H01L25/065 , H01L25/00
摘要： One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
摘要翻译：一个特征涉及至少包括第一集成电路（IC）管芯和第二IC管芯的多芯片模块。第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。第二管芯的有源表面还包括电耦合到I / O节点并且适于保护第二IC管芯免受静电放电（ESD）引起的损坏的熔丝。特别地，保险丝保护第二IC芯片免受可能由于在制造多芯片模块期间将第一裸片电耦合到第二裸片而产生的ESD。在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。多芯片模块封装完成后，保险丝可能会断开。

6. 发明申请

WO2019177709A1 ASYNCHRONOUS INTERRUPT WITH SYNCHRONOUS POLLING AND INHIBIT OPTIONS ON AN RFFE BUS 审中-公开
公开(公告)号：WO2019177709A1
公开(公告)日：2019-09-19
申请号：PCT/US2019/016037
申请日：2019-01-31
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard Dominic , O'SHEA, Helena Deirdre , ROETHIG, Wolfgang , CHUN, Christopher Kong Yee , CHEN, ZhenQi , DAVENPORT, Scott , TAN, Chiew-Guan , CHEN, Wilson , SRIKANTIAH, Umesh
IPC分类号： H04B1/12 , G06F13/42
摘要： Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high- impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

7. 发明申请

WO2017099937A1 SINGLE-LINE PMIC-HOST LOW-LEVEL CONTROL INTERFACE 审中-公开
标题翻译：单线PMIC-HOST低电平控制接口
公开(公告)号：WO2017099937A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/061392
申请日：2016-11-10
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan , CHUN, Chrisotpher Kong Yee , TAN, Chiew-Guan , LEE, Gordon , SUTTON, Todd
IPC分类号： G06F13/42
CPC分类号： H04L47/12 , G06F13/4278 , G06F13/4295 , H04L5/14 , H04L49/109 , H04W28/0221 , H04W52/0229 , Y02D70/122 , Y02D70/26
摘要： System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.
摘要翻译：描述了便于在单个双向线路上的设备之间的信令的系统，方法和设备。在一个示例中，该设备经由单个双向线路将第一设备耦合到第二设备，通过在单个双向线路上从第一设备发起的第一单动态转换指示在第一设备处发起的第一动作的发起并且指示在所述第二设备处发起的通过在所述单个双向线上从所述第二设备向所述第一设备发送第二单个转换的第二动作的发起。在另一示例中，第一设备发起第一动作，通过在单个双向线上生成第一事件来指示第一动作的发起，并且通过观察第二事件在第二设备处发起的第二动作的指示单一的双向线。

8. 发明申请

WO2016137639A1 OUTPUT DRIVER WITH BACK-POWERING PREVENTION 审中-公开
标题翻译：输出驱动器具有备用电源预防
公开(公告)号：WO2016137639A1
公开(公告)日：2016-09-01
申请号：PCT/US2016/014990
申请日：2016-01-26
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , JALILIZEINALI, Reza
IPC分类号： H03K19/003
CPC分类号： H03K17/26 , H03K17/18 , H03K19/00315 , H03K19/00361
摘要： A back-power prevention circuit (205) is provided that protects a buffer transistor (MPl) from back-power during a back-power condition by charging a signal lead (PCLT) coupled to a gate of the buffer transistor (MPl), to a pad voltage (PadSig) and by charging a body (235) of the buffer transistor (MPl) to the pad voltage (PadSig, NW).
摘要翻译：提供了一种背功率防止电路（205），其通过对耦合到缓冲晶体管（MP1）的栅极的信号引线（PCLT）进行充电来在后功率状态期间保护缓冲晶体管（MP1）免于后功率，垫片电压（PadSig），并通过将缓冲晶体管（MP1）的主体（235）充电到焊盘电压（PadSig，NW）。

9. 发明申请

WO2023086243A2 INPUT/OUTPUT (I/O) CIRCUIT WITH DYNAMIC FULL-GATE BOOSTING OF PULL-UP AND PULL-DOWN TRANSISTORS 审中-公开
公开(公告)号：WO2023086243A2
公开(公告)日：2023-05-19
申请号：PCT/US2022/048591
申请日：2022-11-01
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan
IPC分类号： H03K19/003 , H03K19/0185
摘要： An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

10. 发明申请

WO2020046506A1 DYNAMIC POWER SUPPLY SHIFTING 审中-公开
公开(公告)号：WO2020046506A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/043564
申请日：2019-07-26
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson Jianbo , TAN, Chiew-Guan , RAO, Sumit
IPC分类号： H03K19/003 , H03K19/0185
摘要： Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal (102) into a low-voltage signal (135). The high voltage input signal (102) is split into a upper portion (125) and a lower portion (130). The upper portion is coupled to a high input receiver (115) that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

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