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1. 发明申请

WO2006058050A3 SYSTEMS AND METHODS FOR IMPLEMENTING CYCLIC REDUNDANCY CHECKS 审中-公开
公开(公告)号：WO2006058050A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042412
申请日：2005-11-23
申请人： QUALCOMM INCORPORATED , STEELE, Brian , WILEY, George A.
发明人： STEELE, Brian , WILEY, George A.
IPC分类号： G06F11/10 , H03M13/09
摘要： Cyclic redundancy checks to improve link initialization processing and to exchange system error information are described. A cyclic redundancy check (CRC) checker including a unique pattern detector (710), a CRC generator (720), a CRC initializer (730) and a CRC verifier (740) is described. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt (850) of the unique pattern within a data stream received over a digital transmission link such as an MDDI link, the CRC checker checks CRCs (860) without queueing and storing data. The CRC generator system can also intentionally corrupt CRC values to transmit system error information, the CRC generator system including a CRC generator (910), a CRC corrupter (920), and error detector (930) and an error value generator (940).

2. 发明申请

WO2005096594A1 HIGH DATA RATE INTERFACE APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2005096594A1
公开(公告)日：2005-10-13
申请号：PCT/US2005/009944
申请日：2005-03-24
申请人： QUALCOMM Incorporated , ANDERSON, Jon James , STEELE, Brian , WILEY, George A. , SHEKHAR, Shashank
发明人： ANDERSON, Jon James , STEELE, Brian , WILEY, George A. , SHEKHAR, Shashank
IPC分类号： H04L29/06
CPC分类号： H04L67/303 , H04L29/06027 , H04L65/1069 , H04L65/4069 , H04L65/80 , H04L69/18 , H04L69/22 , H04L69/24 , H04M1/72527 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

3. 发明申请

WO2005088939A1 HIGH DATA RATE INTERFACE APPARATUS AND METHOD 审中-公开
标题翻译：高数据速率接口设备和方法
公开(公告)号：WO2005088939A1
公开(公告)日：2005-09-22
申请号：PCT/US2005/008073
申请日：2005-03-10
申请人： QUALCOMM INCORPORATED , ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
发明人： ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
IPC分类号： H04L29/06
CPC分类号： H04L65/80 , H04L29/06027 , H04L65/1069 , H04L65/4069 , H04L69/18 , H04L69/22 , H04M1/72527 , H04N19/89 , H04N21/43615 , H04N21/4363 , Y02D70/00 , Y02D70/122 , Y02D70/144 , Y02D70/166 , Y02D70/26
摘要： A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
摘要翻译：一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并被耦合到客户端通过通信路径。该接口通过短距离“串行”型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，这些电缆特别适用于将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

4. 发明申请

WO2005027467A1 HIGH DATA RATE INTERFACE 审中-公开
标题翻译：高数据速率接口
公开(公告)号：WO2005027467A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/029529
申请日：2004-09-10
申请人： QUALCOMM INCORPORATED , ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
发明人： ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
IPC分类号： H04L29/06
CPC分类号： H04L65/607 , H04L29/06027 , H04L69/14 , H04L69/18 , H04L69/22 , H04L69/24 , H04M1/72527 , Y02D50/30 , Y02D70/00 , Y02D70/122 , Y02D70/144 , Y02D70/26
摘要： A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
摘要翻译：一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并被耦合到客户端通过通信路径。该接口通过短距离“串行”型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，这些电缆特别适用于将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

5. 发明申请

WO2003023587A2 GENERATING AND IMPLEMENTING A COMMUNICATION PROTOCOL AND INTERFACE FOR HIGH DATA RATE SIGNAL TRANSFER 审中-公开
标题翻译：高速数据速率信号传输的通信协议和接口的生成和实现
公开(公告)号：WO2003023587A2
公开(公告)日：2003-03-20
申请号：PCT/US2002/028461
申请日：2002-09-06
申请人： QUALCOMM, INCORPORATED
发明人： ZOU, Qiuzhen , WILEY, George, Alan , STEELE, Brian
IPC分类号： G06F3/00
CPC分类号： H04L25/45 , G06F3/14 , G09G5/006 , G09G5/06 , G09G2370/045 , G09G2370/10 , G09G2370/16 , H04M1/72527 , H04N19/46 , Y02D70/26
摘要： A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
摘要翻译：数据接口，用于使用链接在一起的分组结构在通信路径上在主机和客户机之间传送数字数据，以形成用于传送预先选择的一组数字控制和演示数据的通信协议。信号协议由链路控制器使用，所述链路控制器被配置为生成，发送和接收形成通信协议的分组，并且将数字数据形成为一种或多种类型的数据分组，其中至少一个驻留在主机设备中并且耦合到客户端通过通信路径。该接口通过短距离“串行”接口提供了成本低，功耗低，双向，高速的数据传输机制。型数据链路，它适用于微型连接器和薄型柔性电缆，这些连接器尤其适用于将可穿戴微型显示器等显示器元件连接到便携式计算机和无线通信设备。

6. 发明公开

EP2483757A1 METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR 有权
标题翻译：方法和系统运行的计算机上的低能额外的处理器
公开(公告)号：EP2483757A1
公开(公告)日：2012-08-08
申请号：EP10752677.4
申请日：2010-08-31
申请人： Qualcomm Incorporated
发明人： PYERS, James , WILEY, George , WILLKIE, James J. , STEELE, Brian , NAHATA, Apul , KALIANNAN, Karthik Raj
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122
摘要： A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in off, standby or sleep modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
摘要翻译：一种计算设备，包括低功率辅助处理器，检查作为无线卡或子系统上的处理器，所有这些都能够接管处理代替计算设备的中央处理单元（CPU）的。操作所述计算设备的辅助处理器上从所述计算设备中的电池较少的功率，在辅助处理器模式使能延长的运行英寸当在这种模式下，所述辅助处理器控制的外围设备，并提供了在CPU被去激活，：诸如在断开，待机或睡眠模式的系统功能。在辅助处理器模式中，计算设备可以完成有用的任务，：诸如发送/接收电子邮件，显示电子文档和访问网络，同时从电池汲取最小的功率。在正常操作模式和辅助处理器模式之间的转换可以是对用户透明。这样的计算机可显示上的即时的，并且总是始终连接操作特征。

7. 发明申请

WO2011026084A1 METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR 审中-公开
标题翻译：用于通过低功率ADJUNCT处理器操作计算机的方法和系统
公开(公告)号：WO2011026084A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/047273
申请日：2010-08-31
申请人： QUALCOMM Incorporated , PYERS, James , WILEY, George , WILLKIE, James J. , STEELE, Brian , NAHATA, Apul , KALIANNAN, Karthik Raj
发明人： PYERS, James , WILEY, George , WILLKIE, James J. , STEELE, Brian , NAHATA, Apul , KALIANNAN, Karthik Raj
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3293 , Y02D10/122
摘要： A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in "off," "standby" or "sleep" modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
摘要翻译：计算设备包括能够接管处理代替计算设备的中央处理单元（CPU）的低功率辅助处理器，诸如无线卡或子系统上的处理器。在辅助处理器上操作计算设备从计算设备电池吸取更少的电力，从而能够在辅助处理器模式下进行扩展操作。在此模式下，辅助处理器控制外设，并在CPU被关闭时提供系统功能，例如处于“关闭”，“待机”或“睡眠”模式。在辅助处理器模式中，计算设备可以实现有用的任务，例如发送/接收电子邮件，显示电子文档和访问网络，同时从电池中抽取最小功率。正常操作模式和辅助处理器模式之间的转换可能对用户来说是透明的。这样的计算机可以立即显示，始终处于和始终连接的操作特征。

8. 发明申请

WO2009073250A2 A PACKET STRUCTURE FOR A MOBILE DISPLAY DIGITAL INTERFACE 审中-公开
标题翻译：移动显示数字接口的分组结构
公开(公告)号：WO2009073250A2
公开(公告)日：2009-06-11
申请号：PCT/US2008/063109
申请日：2008-05-08
申请人： QUALCOMM INCORPORATED , STEELE, Brian , WILEY, George, Alan , SHEKHAR, Shashank
发明人： STEELE, Brian , WILEY, George, Alan , SHEKHAR, Shashank
IPC分类号： H04L12/56 , H04N7/24
CPC分类号： H04L69/22 , H04L69/18 , H04W80/02
摘要： A packet structure for a Mobile Display Digital Interface (MDDI) includes a flexible sub-frame length to efficiently transmit large packets. A windowless video stream packet avoids repetitive transmissions of video packets when some parameters are unchanged, saving bandwidth. An enhanced reverse encapsulation packet combines the feature of a separate round trip delay packet with a separate reverse encapsulation packet. A link freeze is used to halt a transmission of a data stream at any point in the transmission and resume the transmission by a host.
摘要翻译：用于移动显示数字接口（MDDI）的分组结构包括有效传输大分组的灵活子帧长度。当一些参数不变时，无窗口视频流数据包避免视频数据包的重复传输，从而节省带宽。增强的反向封装分组将单独的往返延迟分组的特征与单独的反向封装分组相结合。链路冻结用于在传输中的任何点停止数据流的传输，并由主机恢复传输。

9. 发明申请

WO2006058045A2 DIGITAL DATA INTERFACE DEVICE 审中-公开
标题翻译：数字数据接口设备
公开(公告)号：WO2006058045A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/042402
申请日：2005-11-23
申请人： QUALCOMM INCORPORATED , KATIBIAN, Behnam , WILEY, George, A. , STEELE, Brian
发明人： KATIBIAN, Behnam , WILEY, George, A. , STEELE, Brian
IPC分类号： H04J3/12
CPC分类号： H04L7/10 , G09G5/006 , G09G2370/045 , G09G2370/10 , H04L7/048
摘要： The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.
摘要翻译：本发明涉及一种用于通过通信链路以高速率传送数字呈现数据的数字数据接口设备。数字数据接口设备包括消息解释器，内容模块和控制模块。数字数据接口设备可以包括MDDI链路控制器。数字数据接口设备可用于控制诸如照相机，条形码读取器，图像扫描器，音频设备或其他传感器的外围设备。在一个示例中，提供具有具有MDDI链路的相机和数字数据设备接口的蜂窝电话。

10. 发明申请

WO2005122509A1 HIGH DATA RATE INTERFACE APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2005122509A1
公开(公告)日：2005-12-22
申请号：PCT/US2005/019530
申请日：2005-06-03
申请人： QUALCOMM INCORPORATED , ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
发明人： ANDERSON, Jon, James , STEELE, Brian , WILEY, George, A. , SHEKHAR, Shashank
IPC分类号： H04L12/64
CPC分类号： H04L12/6418 , H04L29/06027 , H04L65/1069 , H04L65/4069 , H04L65/80 , H04L67/125 , H04L67/36 , H04L69/329 , H04L2012/6483 , H04M1/72527 , Y02D70/144 , Y02D70/26
摘要： A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

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