专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2015079243A1 ANTENNA AND APPARATUS COMPRISING ANTENNA 审中-公开
标题翻译：天线和装置包括天线
公开(公告)号：WO2015079243A1
公开(公告)日：2015-06-04
申请号：PCT/GB2014/053525
申请日：2014-11-28
申请人： PRAGMATIC PRINTING LTD
发明人： DE OLIVEIRA, Joao
IPC分类号： H01Q1/38 , H01Q1/44 , H01Q7/00 , H01Q1/22 , G08B13/24
CPC分类号： H01Q1/2225 , G06K7/10158 , G06K19/07783 , G08B13/2417 , H01Q1/2216 , H01Q1/38 , H01Q1/44 , H01Q7/00 , H04B5/0081
摘要： An antenna comprises: a first terminal; a second terminal; and a winding, having an inductance, comprising a plurality of turns and connected between the first and second terminals such that a change in magnetic flux linking the winding generates a corresponding voltage between said terminals. The winding comprises a conductive element connected to the first and second terminals and extending around said turns from the first terminal to the second terminal and having a thickness not exceeding Χμm along a length of the conductive element from the first to the second terminal and a width not exceeding Χμm along said length, where X is less than or equal to 10, whereby said conductive element is substantially non-visible to a naked human eye.
摘要翻译：天线包括：第一终端; 第二个终端以及具有电感的绕组，包括多个匝并连接在第一和第二端子之间，使得连接绕组的磁通量的变化在所述端子之间产生相应的电压。所述绕组包括连接到所述第一端子和所述第二端子的导电元件，并且围绕所述匝从所述第一端子延伸到所述第二端子，并且沿着所述导电元件的从所述第一端子到所述第二端子的长度具有不超过Xλ的厚度，沿着所述长度不超过X 1，其中X小于或等于10，由此所述导电元件对于裸眼睛基本上不可见。

2. 发明申请

WO2019220123A1 AND GATES AND CLOCK DIVIDERS 审中-公开
公开(公告)号：WO2019220123A1
公开(公告)日：2019-11-21
申请号：PCT/GB2019/051346
申请日：2019-05-16
申请人： PRAGMATIC PRINTING LTD
发明人： DE OLIVEIRA, Joao
IPC分类号： H03K3/012 , H03K19/094 , H03K19/0944
摘要： An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.

3. 发明申请

WO2019171041A1 MEASUREMENT APPARATUS 审中-公开
公开(公告)号：WO2019171041A1
公开(公告)日：2019-09-12
申请号：PCT/GB2019/050607
申请日：2019-03-05
申请人： PRAGMATIC PRINTING LTD.
发明人： COBB, Brian Hardy , DE OLIVEIRA, Joao , CLARK, Thomas , WILLIAMSON, Kenneth David
IPC分类号： H03M1/60
摘要： Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.

4. 发明申请

WO2015008067A1 ELECTRONIC CIRCUITS 审中-公开
标题翻译：电子电路
公开(公告)号：WO2015008067A1
公开(公告)日：2015-01-22
申请号：PCT/GB2014/052175
申请日：2014-07-16
申请人： PRAGMATIC PRINTING LTD
发明人： DE OLIVEIRA, Joao , WHITE, Scott Darren , RAMSDALE, Catherine
IPC分类号： H03K19/0944
CPC分类号： H03K19/0944 , H03K3/0315 , H03K3/037 , H03K3/356017 , H03K17/16 , H03K19/09441 , H03K19/20 , H03K23/002
摘要： An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
摘要翻译：电子电路包括：输入端; 输出端子; 第一和第二供电轨; 第一，第二，第三和第四场效应晶体管，每个具有第一类型和每个具有相应的栅极，源极和漏极端子的FET; 以及第一和第二载荷。第一FET的源极连接到第一电源轨，第一FET的漏极和第二FET的源极连接到输出端子，第二FET的漏极连接到第二电源轨，栅极第三FET的栅极和第四FET的栅极连接到输入端子，第三FET的漏极连接到第二电源轨，第一负载连接在第一电源轨和第三FET的源极之间，并且第二负载连接在第四FET的漏极和第二电源轨之间。在本发明的一个方面，第一FET的栅极连接到第三FET的源极与第一负载之间的节点，使得第三FET的源极处的电压被施加到第一FET的栅极，并且第二FET的栅极连接到第四FET的漏极和第二负载之间的节点，使得第四FET的漏极处的电压被施加到第二FET的栅极。

5. 发明申请

WO2020128424A1 AN RFID SYSTEM WITH IMPROVED SIGNAL TRANSMISSION CHARACTERISTICS 审中-公开
公开(公告)号：WO2020128424A1
公开(公告)日：2020-06-25
申请号：PCT/GB2019/053409
申请日：2019-12-03
申请人： PRAGMATIC PRINTING LTD.
发明人： DE OLIVEIRA, Joao
IPC分类号： G06K7/10 , G06K19/07
摘要： A RFID (Radio Frequency Identification) system is provided, comprising at least one tag assembly having at least one tag inductance element that is operatively coupled to an integrated circuit (IC). The RFID system further comprises at least one reader assembly having at least one reader inductance element that is configured to operatively and communicatively couple with the tag assembly, and a resonance assembly having at least one first resonance element that is inductively couple able to the at least one tag inductance element and/or at least one second resonance element that is inductively couple able to the at least one reader inductance element, and which is adapted to provide coupled magnetic resonance signal transmission between the reader assembly and the tag assembly.

6. 发明申请

WO2016051192A1 COMPARATOR 审中-公开
标题翻译：比较器
公开(公告)号：WO2016051192A1
公开(公告)日：2016-04-07
申请号：PCT/GB2015/052883
申请日：2015-10-01
申请人： PRAGMATIC PRINTING LTD
发明人： DE OLIVEIRA, Joao
IPC分类号： H03K5/24 , H03K19/094
CPC分类号： H03K5/2481 , H03K5/249 , H03K19/09432
摘要： A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e-) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e-) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal.
摘要翻译：公开了一种比较器，用于将第一输入电压（e +）与第二输入电压（e-）进行比较并产生相应的输出电压（输出）。比较器包括：用于接收第一输入电压的第一输入端（e +）：用于接收第二输入电压的第二输入端（e-）; 用于输出输出电压的输出端（out）; 用于提供第一电源电压的第一电源轨（VCC）; 以及用于提供第二电源电压的第二电源轨（VDD）。所述比较器还包括：跟随器级，包括耦合到所述第一电源轨的第一跟随器级电源端子，耦合到所述第二电源轨的第二跟随器级电源端子，耦合到所述第二输入端子的跟随器级输入端子，用于提供跟随器级输出电压; 以及逆变器级，包括耦合到第一电源轨的第一反相器级电源端子，耦合到跟随器级输出端子的第二反相器级电源端子，耦合到第一输入端子的反相器级输入端子和反相器级输出端子用于提供逆变器级输出电压并耦合到输出端子。

7. 发明授权

EP3202038B1 COMPARATOR 有权
公开(公告)号：EP3202038B1
公开(公告)日：2020-09-16
申请号：EP15782021.8
申请日：2015-10-01
申请人： PragmatIC Printing Ltd
发明人： DE OLIVEIRA, Joao
IPC分类号： H03K5/24 , H03K19/094

8. 发明公开

EP3146296A1 CAPACITIVE DETECTION, ENERGY TRANSFER, AND/OR DATA TRANSFER SYSTEM 有权
标题翻译： KAPAZITIVER NACHWEIS，ENERGIEÜBERTRAGUNGUND / ODERDATENÜBERTRAGUNGSSYSTEM
公开(公告)号：EP3146296A1
公开(公告)日：2017-03-29
申请号：EP15728084.3
申请日：2015-05-26
申请人： Pragmatic Printing Ltd
发明人： DE OLIVEIRA, Joao
IPC分类号： G01D5/241
CPC分类号： G01D5/2412
摘要： A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the moveable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.
摘要翻译：公开了一种系统，其包括基座和至少第一可移动实体，所述第一可移动实体可相对于所述基座移动并且可相对于所述基座至少位于第一位置。基座包括第一基极和第二基极，并且可移动实体包括第一可移动实体电极和第二可移动实体电极。电极被布置成使得当可移动实体处于第一位置时，第一基极和第一可移动实体电极对准以形成第一电容器，并且第二基极和第二可移动实体电极对准以形成第二电容器。第一可移动实体还包括将第一可移动实体电极连接到第二可移动实体电极的第一电阻器，并且基座还包括：信号供给装置，被布置成向第一基极提供时变电信号; 以及信号检测装置，被配置为检测来自第二基极的电信号。

9. 发明公开

EP3837638A1 CAPACITIVELY COUPLED RFID COMMUNICATION 审中-公开
公开(公告)号：EP3837638A1
公开(公告)日：2021-06-23
申请号：EP19753447.2
申请日：2019-08-08
申请人： PragmatIC Printing Ltd
发明人： DE OLIVEIRA, Joao , COBB, Brian , CLARK, Thomas
IPC分类号： G06K19/077 , G06K7/10

10. 发明公开

EP3022843A1 ELECTRONIC CIRCUITS 有权
标题翻译： ELEKTRONISCHE SCHALTUNGEN
公开(公告)号：EP3022843A1
公开(公告)日：2016-05-25
申请号：EP14742323.0
申请日：2014-07-16
申请人： Pragmatic Printing Ltd
发明人： DE OLIVEIRA, Joao , WHITE, Scott Darren , RAMSDALE, Catherine
IPC分类号： H03K19/0944
摘要： An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
摘要翻译：电子电路包括：输入端; 输出端子; 第一和第二供电轨; 第一，第二，第三和第四场效应晶体管，每个具有第一类型和每个具有相应的栅极，源极和漏极端子的FET; 以及第一和第二载荷。第一FET的源极连接到第一电源轨，第一FET的漏极和第二FET的源极连接到输出端子，第二FET的漏极连接到第二电源轨，栅极的第三FET和第四FET的栅极连接到输入端子，第三FET的漏极连接到第二电源轨，第一负载连接在第一电源轨和第三FET的源极之间，并且第二负载连接在第四FET的漏极和第二电源轨之间。在本发明的一个方面，第一FET的栅极连接到第三FET的源极与第一负载之间的节点，使得第三FET的源极处的电压被施加到第一FET的栅极，并且第二FET的栅极连接到第四FET的漏极和第二负载之间的节点，使得第四FET的漏极处的电压被施加到第二FET的栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式