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1. 发明授权

US07779206B2 Cache inspection with inspection bypass feature 有权
标题翻译：具有检查旁路功能的缓存检查
公开(公告)号：US07779206B2
公开(公告)日：2010-08-17
申请号：US11383374
申请日：2006-05-15
申请人： Oliver P. Sohm , Brian Cruickshank , Gary L. Swoboda , Jagadeesh Sankaran
发明人： Oliver P. Sohm , Brian Cruickshank , Gary L. Swoboda , Jagadeesh Sankaran
IPC分类号： G06F11/32 , G06F11/34 , G06F12/08
CPC分类号： G06F12/0888 , G06F11/3648
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to selectively bypass a portion of the information specified by a user of the software and to provide non-bypassed information to the user and not said bypassed portion.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从电路逻辑接收适于从不同高速缓存级别上的高速缓存收集信息的信息，所述缓存中的至少一些信息来自不同缓存级别上的缓存级别有一个共同的地址。软件还使得处理器有选择地绕过由软件的用户指定的信息的一部分，并且向用户提供非旁路信息，而不是旁路部分。

2. 发明授权

US07788642B2 Displaying cache information using mark-up techniques 有权
标题翻译：使用标记技术显示缓存信息
公开(公告)号：US07788642B2
公开(公告)日：2010-08-31
申请号：US11383448
申请日：2006-05-15
申请人： Oliver P. Sohm , Brian Cruickshank , Jagadeesh Sankaran , Gary L. Swoboda
发明人： Oliver P. Sohm , Brian Cruickshank , Jagadeesh Sankaran , Gary L. Swoboda
IPC分类号： G06F9/44
CPC分类号： G06F12/0897 , G06F12/0804
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从适于从不同缓存级别上的高速缓存收集信息的电路逻辑接收信息。至少一些信息来自与公共地址相关联的不同缓存级别上的缓存。处理器还通过图形用户界面（GUI）显示信息。 GUI使用不同于用于显示信息的剩余部分的标记技术来显示信息的一部分。

3. 发明授权

US07739453B2 Providing information associated with a cache 有权
标题翻译：提供与缓存相关联的信息
公开(公告)号：US07739453B2
公开(公告)日：2010-06-15
申请号：US11383459
申请日：2006-05-15
申请人： Oliver P. Sohm , Brian Cruickshank , Gary L. Swoboda , Jagadeesh Sankaran
发明人： Oliver P. Sohm , Brian Cruickshank , Gary L. Swoboda , Jagadeesh Sankaran
IPC分类号： G06F11/32 , G06F11/34 , G06F7/20
CPC分类号： G06F12/122 , G06F12/0897
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从适于从不同高速缓存级别的高速缓存收集信息的电路逻辑接收信息，所述信息与公共地址相关联。软件还使处理器向软件的用户提供信息。信息包括来自不同高速缓存级别之一的与特定高速缓存相关联的缓存级别和高速缓存类型信息。

4. 发明申请

US20060259700A1 PROVIDING INFORMATION ASSOCIATED WITH A CACHE 有权
标题翻译：提供与缓存相关的信息
公开(公告)号：US20060259700A1
公开(公告)日：2006-11-16
申请号：US11383459
申请日：2006-05-15
申请人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran
发明人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/122 , G06F12/0897
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从适于从不同高速缓存级别的高速缓存收集信息的电路逻辑接收信息，所述信息与公共地址相关联。软件还使得处理器向软件的用户提供信息。信息包括来自不同高速缓存级别之一的与特定高速缓存相关联的缓存级别和高速缓存类型信息。

5. 发明申请

US20060259698A1 DISPLAYING CACHE INFORMATION USING MARK-UP TECHNIQUES 有权
标题翻译：使用标记技术显示缓存信息
公开(公告)号：US20060259698A1
公开(公告)日：2006-11-16
申请号：US11383448
申请日：2006-05-15
申请人： Oliver Sohm , Brian Cruickshank , Jagadeesh Sankaran , Gary Swoboda
发明人： Oliver Sohm , Brian Cruickshank , Jagadeesh Sankaran , Gary Swoboda
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从适于从不同缓存级别上的高速缓存收集信息的电路逻辑接收信息。至少一些信息来自与公共地址相关联的不同缓存级别上的缓存。处理器还通过图形用户界面（GUI）显示信息。 GUI使用不同于用于显示信息的剩余部分的标记技术来显示信息的一部分。

6. 发明申请

US20060259696A1 DETERMINING DIFFERENCES BETWEEN CACHED COPIES OF AN ADDRESS 审中-公开
标题翻译：确定地址的高速缓存副本之间的差异
公开(公告)号：US20060259696A1
公开(公告)日：2006-11-16
申请号：US11383385
申请日：2006-05-15
申请人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran , Bradley Caldwell
发明人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran , Bradley Caldwell
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0859
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to determine a difference between the information from caches on different cache levels associated with the common address and to provide the difference to a user of the software.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从不同高速缓存级别的高速缓存中接收来自与公共地址相关联的不同缓存级别上的高速缓存中的信息中的至少一些信息。该软件还使得处理器确定来自与公共地址相关联的不同高速缓存级别上的高速缓存的信息之间的差异，并且向软件的用户提供差异。

7. 发明申请

US20060259694A1 BYPASSING CACHE INFORMATION 有权
标题翻译：绕过高速缓存的信息
公开(公告)号：US20060259694A1
公开(公告)日：2006-11-16
申请号：US11383374
申请日：2006-05-15
申请人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran
发明人： Oliver Sohm , Brian Cruickshank , Gary Swoboda , Jagadeesh Sankaran
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0888 , G06F11/3648
摘要： An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to selectively bypass a portion of the information specified by a user of the software and to provide non-bypassed information to the user and not said bypassed portion.
摘要翻译：一种包含软件的信息载体介质，所述软件在由处理器执行时使所述处理器从电路逻辑接收适于从不同高速缓存级别上的高速缓存收集信息的信息，所述缓存中的至少一些信息来自不同缓存级别上的缓存级别有一个共同的地址。软件还使得处理器有选择地绕过由软件的用户指定的信息的一部分，并且向用户提供非旁路信息，而不是旁路部分。

8. 发明申请

US20090006037A1 Accurate Benchmarking of CODECS With Multiple CPUs 审中-公开
标题翻译：使用多个CPU对CODECS进行准确的基准测试
公开(公告)号：US20090006037A1
公开(公告)日：2009-01-01
申请号：US12131563
申请日：2008-06-02
申请人： Jagadeesh Sankaran
发明人： Jagadeesh Sankaran
IPC分类号： G06F15/00
CPC分类号： H04N19/436 , H04N19/61
摘要： An accurate and simple benchmarking method for multiple processor systems. Instead of a central timer as used in the prior art, a counter is implemented in each processor that counts the processor's clock cycles. The counter may be read after the processor's completes a benchmark task. This eliminates the timing skew common in the prior art.
摘要翻译：一种用于多处理器系统的准确和简单的基准测试方法。代替现有技术中使用的中央定时器，在每个处理器中实现对处理器的时钟周期进行计数的计数器。在处理器完成基准任务之后，可能会读取计数器。这消除了现有技术中常见的定时偏移。

9. 发明授权

US06876317B2 Method of context based adaptive binary arithmetic decoding with two part symbol decoding 有权
公开(公告)号：US06876317B2
公开(公告)日：2005-04-05
申请号：US10858140
申请日：2004-06-01
申请人： Jagadeesh Sankaran
发明人： Jagadeesh Sankaran
IPC分类号： H03M7/00 , H03M7/34 , H03M7/40
CPC分类号： H03M7/4006
摘要： This invention is method of decoding a context based adaptive binary arithmetic encoded bit stream. The invention determines a maximum number of iterations for decoding a next symbol. This preferably employs a left most bit detect command. The invention considers the bit stream bit by bit until detection of a bit having a first digital state of the maximum number of iterations. If the maximum number of iterations occurs first, the invention decodes the considered bits. If a bit having the first digital state occurs first, the invention selects a number of next bits from the bit stream dependent upon the determined position within the coding table and decodes a symbol corresponding to the maximum number of bits and the selected number of next bits. The invention preferably pre-calculates an order symbol contexts corresponding to an order of determination of a code tree encompassing all possible codes and decodes symbols dependent upon a current context within the pre-calculated.

10. 发明申请

US20050058358A1 Method for planar processing of wavelet zero-tree data 审中-公开
标题翻译：小波零树数据的平面处理方法
公开(公告)号：US20050058358A1
公开(公告)日：2005-03-17
申请号：US10883872
申请日：2004-07-02
申请人： Joseph Zbiciak , Jagadeesh Sankaran
发明人： Joseph Zbiciak , Jagadeesh Sankaran
IPC分类号： G06K9/36
CPC分类号： H04N19/647
摘要： This invention is a method of embedded zero-tree wavelet encoding that operates on planarized wavelet coefficient data. Following wavelet transformation of image data, the wavelet coefficients are transformed into bit plane form. The threshold comparisons are thus converted into determination whether a corresponding bit in a bit plane data word corresponding to the threshold is “1” or “0”. The reduction of the threshold occurs by consideration of the bit plane data for the next most significant bit. Zero-tree node determinations are made by a bottom up ANDing of the bits for all descendant wavelet coefficients. This technique makes better use of memory bandwidth, cache and data processing capability by operating on only the needed data.
摘要翻译：本发明是对平坦化小波系数数据进行操作的嵌入式零树小波编码方法。在图像数据的小波变换之后，小波系数被转换成位平面形式。因此，阈值比较被转换为确定与阈值相对应的位平面数据字中的对应位是“1”还是“0”。通过考虑下一个最高有效位的位平面数据来发生阈值的减小。零树节点确定是通过对所有后代小波系数的比特的自下而上的AND进行的。该技术通过仅对所需数据进行操作，从而更好地利用存储器带宽，缓存和数据处理能力。

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