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    • 2. 发明授权
    • Electronic timepiece digital display drive circuit
    • 电子钟表数字显示驱动电路
    • US4122661A
    • 1978-10-31
    • US767094
    • 1977-02-09
    • Masuo Tsuji
    • Masuo Tsuji
    • G04G9/00G04C3/00
    • G04G9/0047
    • An electronic timepiece having detecting and control circuitry for preventing a digital display from being driven by a DC energizing signal is provided. The detecting and controlling circuitry is coupled intermediate the decoder circuitry and driving circuitry in an electronic timepiece digital display arrangement and detects the presence or absence of an intermediate frequency signal being produced by the timekeeping circuitry and applied to the driver circuitry to effect AC driving of the digital display. In response to detecting the absence of an intermediate frequency signal applied to the driver circuitry, the detecting and controlling circuit prevents the decoder circuitry from applying to the driver circuitry decoded timekeeping signals for effecting driving of the digital display, and thereby prevents inadvertent DC driving of the digital display.
    • 提供具有用于防止数字显示被DC通电信号驱动的检测和控制电路的电子钟表。 检测和控制电路被耦合在电子钟表数字显示装置中的解码器电路和驱动电路之间,并且检测由计时电路产生的中频信号的存在或不存在,并被施加到驱动器电路以实现 数字显示。 响应于检测到没有施加到驱动器电路的中频信号,检测和控制电路防止解码器电路施加到驱动器电路解码的计时信号以实现数字显示器的驱动,从而防止无意的DC驱动 数字显示。
    • 4. 发明授权
    • Electronic digital display timepiece correction device
    • 电子数字显示时钟校正装置
    • US3953963A
    • 1976-05-04
    • US496250
    • 1974-08-09
    • Izuhiko NishimuraMasuo Tsuji
    • Izuhiko NishimuraMasuo Tsuji
    • G04G5/00G04G5/04G04C3/00
    • G04G5/04
    • An electronic digital display timepiece having a locking switch to prevent inadvertent correction of the timepiece, the locking switch being adapted to effect setting of at least one of the digits of time displayed. The electronic timepiece includes a quartz crystal oscillator circuit for producing high frequency time standard signals and a divider circuit including a plurality of divider stages adapted to produce low frequency timekeeping signals in response to said high frequency time standard signals. A display is associated with each of the plurality of divider stages in order to display digits of time in response to the low frequency timekeeping signals counted thereby. The count of certain of the divider stages may be corrected by correction switches provided a locking switch is first displaced from a locking mode to release mode. The locking switch is coupled to at least one divider stage not having a correction switch coupled thereto through circuitry effecting a setting of the divider stage by the operation of said locking switch.
    • 一种电子数字显示钟表,其具有锁定开关,以防止钟表的无意的校正,所述锁定开关适于实现所显示的时间的至少一个数字的设定。 该电子钟表包括用于产生高频时间标准信号的石英晶体振荡器电路和包括多个分频器的分频器电路,该分频器电路适于响应于所述高频时间标准信号产生低频计时信号。 显示器与多个分频器级中的每一个相关联,以便响应于由此计数的低频计时信号显示时间的数字。 某些分频器级的计数可以通过校正开关来校正,只要锁定开关首先从锁定模式移位到释放模式。 锁定开关耦合到至少一个分频器级,其不具有通过所述锁定开关的操作实现分频器级的设置的电路与其耦合的校正开关。
    • 5. 发明授权
    • Semiconductor device
    • 半导体器件
    • US5517041A
    • 1996-05-14
    • US50119
    • 1993-06-25
    • Kensuke ToriiYasuhiro OguchiYasuhisa HirabayashiMasuo Tsuji
    • Kensuke ToriiYasuhiro OguchiYasuhisa HirabayashiMasuo Tsuji
    • H01L27/118H01L27/10
    • H01L27/11807
    • Four gate electrodes of an n-type basic cell of a gate array are essentially oriented in a circular tangential direction of a radius relative to the center point Q of a cell. The electrodes have an upper and lower and a right and left symmetrical layout arrangement relative to the cell upper and lower center line and left and right center line. As a consequence, adjacent gate electrodes are positioned in a .+-.90.degree. rotating symmetry. Each gate electrode has wiring connection areas on both ends. The wiring connection areas overlap the pre-rotation wiring connection areas by a .+-.90.degree. rotation of the cell. Because the gate electrodes are essentially oriented along the circumference direction, the source and the drain are separated in the radial direction of the center of the cell. The wiring connection areas are not concentrated at the center of the cell, and this improves the wiring capabilities within the cell. In addition, because each end of the gate electrodes has an equal positional relationship relative to the center of the cell, the gate electrodes may have wiring connection areas not only on one end, but on both ends. This improves the wiring capability of each gate. The p-type basic cell has the same structure as the n-type basic cell.
    • PCT No.PCT / JP92 / 01119 Sec。 371日期:1993年6月25日 102(e)日期1993年6月25日PCT提交1992年9月2日PCT公布。 出版物WO93 / 05537 日期:1993年3月18日。门阵列的n型基本单元的四个栅电极基本上相对于单元的中心点Q的圆形切线方向取向。 电极具有相对于电池上下中心线和左右中心线的上下左右对称布局布置。 因此,相邻的栅电极位于旋转对称的+/- 90°。 每个栅电极在两端都有接线连接区域。 布线连接区域与预旋转布线连接区域重叠,单元格旋转+/- 90°。 因为栅电极基本上沿着圆周方向取向,源极和漏极在电池的中心的径向方向上被分开。 接线连接区域不集中在电池的中心,这样可以提高电池内的接线能力。 此外,因为栅电极的每一端相对于单元的中心具有相等的位置关系,所以栅电极可以不仅在一端而且在两端具有布线连接区域。 这提高了每个门的接线能力。 p型基本单元具有与n型基本单元相同的结构。