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1. 发明授权

US08067211B2 Method for production of L-glutamine 有权
标题翻译： L-谷氨酰胺的生产方法
公开(公告)号：US08067211B2
公开(公告)日：2011-11-29
申请号：US12159156
申请日：2006-12-27
申请人： Mikiro Hayashi , Masaki Maeda , Yoshiyuki Yonetani
发明人： Mikiro Hayashi , Masaki Maeda , Yoshiyuki Yonetani
IPC分类号： C12P13/14 , C12N1/20 , C07H21/04
CPC分类号： C12N9/93 , C12P13/14
摘要： A polypeptide comprising an amino acid sequence in which one or more amino acids are deleted, substituted or added in the amino acid sequence of a glutamine synthetase 2 derived from a microorganism belonging to a coryneform bacterium, wherein the coryneform bacterium producing the polypeptide has L-glutamine productivity, a DNA encoding the polypeptide, a recombinant DNA comprising the DNA, a microorganism comprising the DNA or the recombinant DNA, and a process for producing L-glutamine using the microorganism are provided.
摘要翻译：一种多肽，其包含氨基酸序列，其中一个或多个氨基酸被缺失，取代或添加在衍生自属于棒状杆菌型细菌的微生物的谷氨酰胺合成酶2的氨基酸序列中，其中产生多肽的棒状细菌具有L- 谷氨酰胺生产力，编码多肽的DNA，包含DNA的重组DNA，包含DNA或重组DNA的微生物，以及使用该微生物生产L-谷氨酰胺的方法。

2. 发明申请

US20100184163A1 METHOD FOR PRODUCTION OF L-GLUTAMINE 有权
标题翻译： L-谷氨酰胺的生产方法
公开(公告)号：US20100184163A1
公开(公告)日：2010-07-22
申请号：US12159156
申请日：2006-12-27
申请人： Mikiro Hayashi , Masaki Maeda , Yoshiyuki Yonetani
发明人： Mikiro Hayashi , Masaki Maeda , Yoshiyuki Yonetani
IPC分类号： C12N1/20 , C07H21/04 , C12N9/00 , C12P13/14
CPC分类号： C12N9/93 , C12P13/14
摘要： A polypeptide comprising an amino acid sequence in which one or more amino acids are deleted, substituted or added in the amino acid sequence of a glutamine synthetase 2 derived from a microorganism belonging to a coryneform bacterium, wherein the coryneform bacterium producing the polypeptide has L-glutamine productivity, a DNA encoding the polypeptide, a recombinant DNA comprising the DNA, a microorganism comprising the DNA or the recombinant DNA, and a process for producing L-glutamine using the microorganism are provided.
摘要翻译：一种多肽，其包含氨基酸序列，其中一个或多个氨基酸被缺失，取代或添加在衍生自属于棒状杆菌型细菌的微生物的谷氨酰胺合成酶2的氨基酸序列中，其中产生多肽的棒状细菌具有L- 谷氨酰胺生产力，编码多肽的DNA，包含DNA的重组DNA，包含DNA或重组DNA的微生物，以及使用该微生物生产L-谷氨酰胺的方法。

3. 发明授权

US08058037B2 Protein and DNA encoding the protein 失效
标题翻译：编码蛋白质的蛋白质和DNA
公开(公告)号：US08058037B2
公开(公告)日：2011-11-15
申请号：US12095244
申请日：2006-11-29
申请人： Shin-ichi Hashimoto , Yoshiyuki Yonetani , Masaki Maeda
发明人： Shin-ichi Hashimoto , Yoshiyuki Yonetani , Masaki Maeda
IPC分类号： C12P7/00 , C12P7/02
CPC分类号： C12P7/62 , C12N9/0006 , C12P7/42 , C12P17/06
摘要： The present invention provides a protein comprising the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3 (except for proteins of the amino acid sequences as shown in SEQ ID NOS: 4 to 6), and a process for industrially advantageously producing a compound that inhibits HMG-CoA reductase and has an action to decrease serum cholesterol, using DNA encoding the protein comprising the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3 (except for DNA encoding the protein comprising the amino acid sequence as shown in SEQ ID NO: 4).
摘要翻译：本发明提供了包含SEQ ID NO：1〜3中任一项所示的氨基酸序列的蛋白质（除了SEQ ID NO：4〜6所示的氨基酸序列的蛋白质）和工业上的工序有利地产生抑制HMG-CoA还原酶并具有降低血清胆固醇的作用的化合物，使用编码包含SEQ ID NO：1至3中任一项所示的氨基酸序列的蛋白的DNA（除了编码包含如SEQ ID NO：4所示的氨基酸序列）。

4. 发明申请

US20100062486A1 NOVEL PROTEIN AND DNA ENCODING THE PROTEIN 失效
标题翻译：新蛋白和DNA编码蛋白
公开(公告)号：US20100062486A1
公开(公告)日：2010-03-11
申请号：US12095244
申请日：2006-11-29
申请人： Shin-ichi Hashimoto , Yoshiyuki Yonetani , Masaki Maeda
发明人： Shin-ichi Hashimoto , Yoshiyuki Yonetani , Masaki Maeda
IPC分类号： C12P21/02 , C07K14/00 , C07H21/04 , C12N1/21 , C07C69/76 , C12P7/62 , C07D315/00
CPC分类号： C12P7/62 , C12N9/0006 , C12P7/42 , C12P17/06
摘要： The present invention provides a protein comprising the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3 (except for proteins of the amino acid sequences as shown in SEQ ID NOS: 4 to 6), and a process for industrially advantageously producing a compound that inhibits HMG-CoA reductase and has an action to decrease serum cholesterol, using DNA encoding the protein comprising the amino acid sequence as shown in any one of SEQ ID NOS: 1 to 3 (except for DNA encoding the protein comprising the amino acid sequence as shown in SEQ ID NO: 4).
摘要翻译：本发明提供了包含SEQ ID NO：1〜3中任一项所示的氨基酸序列的蛋白质（除了SEQ ID NO：4〜6所示的氨基酸序列的蛋白质）和工业上的工序有利地产生抑制HMG-CoA还原酶并具有降低血清胆固醇的作用的化合物，使用编码包含SEQ ID NO：1至3中任一项所示的氨基酸序列的蛋白的DNA（除了编码包含如SEQ ID NO：4所示的氨基酸序列）。

5. 发明授权

US09401039B2 Image processing device, image processing method, program, and integrated circuit 有权
标题翻译：图像处理装置，图像处理方法，程序和集成电路
公开(公告)号：US09401039B2
公开(公告)日：2016-07-26
申请号：US13636437
申请日：2012-05-17
申请人： Masaki Maeda , Naoki Ootani , Kazuhiro Nomura
发明人： Masaki Maeda , Naoki Ootani , Kazuhiro Nomura
IPC分类号： G06T15/08 , G06T15/20 , H04N13/00
CPC分类号： G06T15/08 , G06T15/205 , H04N13/111 , H04N13/128
摘要： A depth image conversion unit moves an edge location in an input depth image towards a background. A pixel shift unit generates an image from a different viewpoint by horizontally shifting coordinates of each pixel in an image based on a converted depth image. A pixel interpolation unit interpolates a missing pixel region yielded by pixel shifting.
摘要翻译：深度图像转换单元将输入深度图像中的边缘位置移动到背景。像素移位单元基于转换的深度图像水平移动图像中的每个像素的坐标，从不同的视点生成图像。像素内插单元内插由像素移位产生的缺失像素区域。

6. 发明授权

US08220607B2 Torque limiter-incorporating one-way clutch 有权
标题翻译：扭矩限制器 - 内置单向离合器
公开(公告)号：US08220607B2
公开(公告)日：2012-07-17
申请号：US11905064
申请日：2007-09-27
申请人： Hajime Watanabe , Hideki Fujiwara , Tomoya Yamatani , Masaki Maeda
发明人： Hajime Watanabe , Hideki Fujiwara , Tomoya Yamatani , Masaki Maeda
IPC分类号： F16D41/067 , F16D43/20 , F16D7/10
CPC分类号： F16D41/064 , F16D41/067
摘要： A length of each pocket of a cage in a circumferential direction is smaller than the sum of an outer diameter of a roller and a free length of a coil spring. The cage can rotate relative to an inner ring having cam surfaces in accordance with revolution of the rollers in an overload-applied condition, and the cage can not rotate in a direction opposite to a direction of revolution of the rollers in the overload-applied condition.
摘要翻译：保持架在圆周方向上的每个袋的长度小于辊的外径和螺旋弹簧的自由长度的总和。保持架可以相对于具有凸轮表面的内圈相对于过载施加状态下的辊的旋转而旋转，并且保持架不能在过载施加条件下沿与辊的旋转方向相反的方向旋转。

7. 发明授权

US07996657B2 Reconfigurable computing circuit 有权
标题翻译：可重构计算电路
公开(公告)号：US07996657B2
公开(公告)日：2011-08-09
申请号：US12105551
申请日：2008-04-18
申请人： Masaki Maeda , Takahiro Ichinomiya
发明人： Masaki Maeda , Takahiro Ichinomiya
IPC分类号： G06F7/38 , G06F9/00
CPC分类号： G06F15/7867
摘要： A reconfigurable computing circuit for reducing the amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block 2010, reg setting data selecting unit 3400 selects either a value stored in reg setting data storage unit 3000 or an initial value output from data reg data generating unit 4000, based on the information stored in reg type managing unit 1100 that indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit 1000. Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.
摘要翻译：一种可重配置计算电路，用于减少存储在数据寄存器中的伪数据的数量，这是当配置信息总线和扫描链共享布线时所需要的。当数据被存储在重构计算块2010中构成扫描链的数据寄存器和配置寄存器中时，寄存器设置数据选择单元3400选择存储在寄存器设置数据存储单元3000中的值或从数据寄存器数据生成产生的初始值单元4000，基于存储在寄存器类型管理单元1100中的信息，其指示扫描链中的寄存器的类型和寄存器的连接顺序，并且在扫描/重新配置控制的控制下将所选择的值依次输出到扫描链单元1000.扫描链中的每个寄存器然后将存储在其中的数据顺序地移动到扫描链中的下一个寄存器。

8. 发明申请

US20090307470A1 MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT 有权
标题翻译：具有动态重构逻辑电路的多线程处理器
公开(公告)号：US20090307470A1
公开(公告)日：2009-12-10
申请号：US12093884
申请日：2006-11-21
申请人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
发明人： Masaki Maeda , Hideshi Nishida , Yorihiko Wakayama
IPC分类号： G06F9/318
CPC分类号： G06F15/7867
摘要： A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.
摘要翻译：根据本发明的处理器在分配给它的每个时间段周期性地执行多个线程。处理器为每个线程存储操作单元的配置信息。每个线程使得执行不同的预定数量的操作单元串联，并且在分配给当前线程的时间段内，基于存储的一条配置信息，连续地重新配置已经完成其最后操作的操作单元对应于下一个线程的操作单元，并且使具有当前线程的配置的操作单元并行执行，以及（ii）具有下一个线程的配置的操作单元。

9. 发明申请

US20080046688A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046688A1
公开(公告)日：2008-02-21
申请号：US11896369
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F15/80 , G06F9/315
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

10. 发明授权

US07281117B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07281117B2
公开(公告)日：2007-10-09
申请号：US10668358
申请日：2003-09-24
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302 , G06F9/318
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

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