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1. 发明授权

US08791521B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08791521B2
公开(公告)日：2014-07-29
申请号：US13423664
申请日：2012-03-19
申请人： Koji Nakahara , Kazuhiro Matsuo , Masayuki Tanaka , Hirofumi Iikawa
发明人： Koji Nakahara , Kazuhiro Matsuo , Masayuki Tanaka , Hirofumi Iikawa
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.
摘要翻译：半导体器件包括在电荷存储层和控制电极层之间形成的电极间绝缘膜。电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。电极间绝缘膜包括：第一堆叠，其包括介于第一和第二氧化硅膜之间的第一氮化硅膜或高介电常数膜，或包括第二高介电常数膜和第三氧化硅膜的第二堆叠，形成在控制电极层和第一或第二堆叠之间的第二氮化硅膜。在第三区域中，第二氮化硅膜比第一区域相对薄。

2. 发明授权

US08525252B2 Nonvolatile semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US08525252B2
公开(公告)日：2013-09-03
申请号：US13233788
申请日：2011-09-15
申请人： Kenichiro Toratani , Masayuki Tanaka , Kazuhiro Matsuo
发明人： Kenichiro Toratani , Masayuki Tanaka , Kazuhiro Matsuo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L27/11582 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.

3. 发明申请

US20100308393A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100308393A1
公开(公告)日：2010-12-09
申请号：US12722111
申请日：2010-03-11
申请人： Kazuhiro Matsuo , Masayuki Tanaka
发明人： Kazuhiro Matsuo , Masayuki Tanaka
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/40114
摘要： A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film.
摘要翻译：一种半导体器件，包括具有通过元件隔离绝缘膜隔离的有源区的半导体衬底; 形成在位于有源区上的栅极绝缘膜上的浮栅电极膜; 在所述元件隔离绝缘膜的上表面上方形成的电极间绝缘膜，以及所述浮栅电极膜的上表面和侧壁，所述电极间绝缘膜由多层膜构成，所述多个膜层包括介电常数等于或等于大于氮化硅膜; 形成在电极间绝缘膜上的控制栅极电极膜; 以及在所述浮栅电极膜的上表面和所述电极间绝缘膜之间形成的氧化硅膜; 其中，电极间绝缘膜的高电介质膜与浮栅电极膜的侧壁直接接触。

4. 发明授权

US07812391B2 Nonvolatile semiconductor memory device and method of fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07812391B2
公开(公告)日：2010-10-12
申请号：US12354200
申请日：2009-01-15
申请人： Kazuhiro Matsuo , Masayuki Tanaka , Atsuhiro Suzuki
发明人： Kazuhiro Matsuo , Masayuki Tanaka , Atsuhiro Suzuki
IPC分类号： H01L21/76
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/94
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å.
摘要翻译：非易失性半导体存储器件包括：半导体衬底，具有由以形成在衬底的表面中的预定间隔分开形成的多个沟槽分开形成的多个有源区;形成在衬底的上表面上的第一栅极绝缘膜，区域，通过依次沉积形成在栅极绝缘膜的上表面上的电荷存储层，第二栅极绝缘膜和控制栅极绝缘膜而形成的存储单元晶体管的栅电极，每个区域中埋设的元件隔离绝缘膜沟槽，并且由涂覆型氧化物膜形成，并且在半导体衬底和元件隔离绝缘膜之间的边界上形成在每个沟槽内的绝缘膜，所述绝缘膜包含非转移金属原子并且具有不大于5的膜厚度。

5. 发明申请

US20090152618A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20090152618A1
公开(公告)日：2009-06-18
申请号：US12333983
申请日：2008-12-12
申请人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
发明人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层，形成在第二绝缘层上的控制电极层。第二绝缘层包括第一氧化硅膜，形成在第一氧化硅膜上并具有不小于7的相对介电常数的中间绝缘膜和形成在中间绝缘膜上的第二氧化硅膜。至少在第一或第二氧化硅膜或第一氧化硅膜和中间绝缘膜之间的边界或第二氧化硅膜和中间绝缘膜之间的边界上形成电荷陷阱层。

6. 发明申请

US20130240978A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130240978A1
公开(公告)日：2013-09-19
申请号：US13601372
申请日：2012-08-31
申请人： Masayuki TANAKA , Kazuhiro Matsuo
发明人： Masayuki TANAKA , Kazuhiro Matsuo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11521
摘要： According to one embodiment, a nonvolatile semiconductor memory device has a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control electrode formed on the second insulating film. In the nonvolatile semiconductor memory device, the second insulating film has a laminated structure that has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film, a first atom is provided at an interface between the first silicon oxide film and the first silicon nitride film, and/or at an interface between the second silicon oxide film and the first silicon nitride film, and the first atom is selected from the group consisting of aluminum, boron, and alkaline earth metals.
摘要翻译：根据一个实施例，非易失性半导体存储器件具有半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及控制电极形成在第二绝缘膜上。在非易失性半导体存储器件中，第二绝缘膜具有层叠结构，该叠层结构具有第一氧化硅膜，第一氮化硅膜和第二氧化硅膜，第一原子设置在第一氧化硅膜和/或在第二氧化硅膜和第一氮化硅膜之间的界面处，并且第一原子选自铝，硼和碱土金属。

7. 发明申请

US20120299083A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120299083A1
公开(公告)日：2012-11-29
申请号：US13233788
申请日：2011-09-15
申请人： Kenichiro Toratani , Masayuki Tanaka , Kazuhiro Matsuo
发明人： Kenichiro Toratani , Masayuki Tanaka , Kazuhiro Matsuo
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L27/11582 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括半导体区域，设置在半导体区域上方的隧道绝缘体，设置在隧道绝缘体上方的电荷存储绝缘体，设置在电荷存储绝缘体上方的块绝缘体，设置在上述所述块绝缘体和包括金属元件的界面区域，所述界面区域设置在从所述半导体区域和所述隧道绝缘体之间的一个界面处，所述隧道绝缘体和所述电荷存储绝缘体，所述电荷存储绝缘体和所述块状绝缘体，和块绝缘体和控制栅电极。

8. 发明授权

US08008707B2 Nonvolatile semiconductor memory device provided with charge storage layer in memory cell 有权
标题翻译：在存储单元中设置有电荷存储层的非易失性半导体存储器件
公开(公告)号：US08008707B2
公开(公告)日：2011-08-30
申请号：US12333983
申请日：2008-12-12
申请人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
发明人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层和形成在第二绝缘层上的控制电极绝缘层。第二绝缘层包括在电荷存储层上形成的第一氧化硅膜，形成在第一氧化硅膜上的氮化硅膜，形成在氮化硅膜上的金属氧化物膜，以及形成在金属氧化物膜上的氮化物膜。金属氧化物膜的相对介电常数不小于7。

9. 发明授权

US08742487B2 Nonvolatile semiconductor memory device provided with charge storage layer in memory cell 有权
标题翻译：在存储单元中设置有电荷存储层的非易失性半导体存储器件
公开(公告)号：US08742487B2
公开(公告)日：2014-06-03
申请号：US13207149
申请日：2011-08-10
申请人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
发明人： Kazuhiro Matsuo , Masayuki Tanaka , Takeo Furuhata , Koji Nakahara
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer and including a first high dielectric insulating film which has a higher relative permittivity than a silicon nitride film and a second high dielectric insulating film which has a higher relative permittivity than a silicon nitride film, the first and second high dielectric insulating films being structured so that a silicon oxide film is interposed between them, a control electrode formed on the second insulation layer, a first portion formed between the charge storage layer and the second insulation layer and containing silicon and nitrogen, and a second portion containing silicon and oxygen and located between the charge storage layer and the second insulation layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层，并且包括第一高介电绝缘膜，具有比氮化硅膜更高的相对介电常数的相对介电常数和比氮化硅膜具有更高的相对介电常数的第二高介电绝缘膜，第一和第二高介电绝缘膜被构造成在它们之间插入氧化硅膜，形成在所述第二绝缘层上的控制电极，形成在所述电荷存储层和所述第二绝缘层之间并且包含硅和氮的第一部分，以及位于所述电荷存储层和所述第二绝缘层之间的含有硅和氧的第二部分。

10. 发明授权

US08471326B2 Semiconductor memory device and manufacturing method of semiconductor memory device 失效
标题翻译：半导体存储器件及半导体存储器件的制造方法
公开(公告)号：US08471326B2
公开(公告)日：2013-06-25
申请号：US13049573
申请日：2011-03-16
申请人： Koji Nakahara , Kazuhiro Matsuo , Masayuki Tanaka
发明人： Koji Nakahara , Kazuhiro Matsuo , Masayuki Tanaka
IPC分类号： H01L21/762 , H01L27/115
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/11539 , H01L27/11541 , H01L27/11543
摘要： According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.
摘要翻译：根据一个实施例，半导体衬底包括单元区域和外围电路区域，在单元区域和外围电路区域中的半导体衬底上形成第一电介质膜，在第一电介质膜上形成第一导电膜单元区域和外围电路区域，在单元区域中的第一导电膜上形成第一导电膜电介质膜，在外围电路的第一导电膜上形成第二导电膜电介质膜区域，其膜厚度大于第一导电膜电介质膜，并且第二导电膜形成在电池区域中的第一导电膜电介质膜上，第二导电膜电介质膜在外围电路区域。

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