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1. 发明授权

US06977941B2 Shared buffer type variable length packet switch 失效
标题翻译：共享缓冲区类型可变长度分组交换机
公开(公告)号：US06977941B2
公开(公告)日：2005-12-20
申请号：US09791791
申请日：2001-02-26
申请人： Masami Takahashi , Akio Makimoto , Takahiko Kozaki , Takayuki Kanno , Yasuo Oginuma , Kaori Nakayama , Mitsuhiro Wada , Norihiko Moriwaki , Masumi Fukano , Yusho Futami
发明人： Masami Takahashi , Akio Makimoto , Takahiko Kozaki , Takayuki Kanno , Yasuo Oginuma , Kaori Nakayama , Mitsuhiro Wada , Norihiko Moriwaki , Masumi Fukano , Yusho Futami
IPC分类号： H04L12/56 , G06F12/00
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/40
摘要： A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.
摘要翻译：一种分组交换机，具有以固定长度数据块单位为基础将从每个输入线路接收的可变长度分组写入共享缓冲存储器的结构，其中缓冲器控制器为每个输入线路形成输入队列，并且当最后数据可变长度分组的块被登记在输入队列中，将用于输入队列的链接地址列表链接到对应于一个或多个分组目的地输出线的一个或多个输出队列。

2. 发明授权

US06611527B1 Packet switching apparatus with a common buffer 失效
标题翻译：具有公共缓冲区的分组交换设备
公开(公告)号：US06611527B1
公开(公告)日：2003-08-26
申请号：US09497210
申请日：2000-02-03
申请人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
发明人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/608 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684
摘要： A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
摘要翻译：在具有共享缓冲器的交换机中执行的地址管理中，将多个地址链分配给每个这样的流作为输出线，优先级控制等。每个地址链具有写入地址寄存器20和读取地址寄存器30.开关还具有分配指示器22，用于将流中的单元分配到多个地址链和写入地址寄存器选择器21 作为用于从多个地址链读取分组的读指针32和读地址寄存器选择器31，以便通过使用这些多个地址链的流水线读取分组。

3. 发明授权

US06507584B1 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06507584B1
公开(公告)日：2003-01-14
申请号：US09193414
申请日：1998-11-18
申请人： Norihiko Moriwaki , Takahiko Kozaki , Takaaki Toyama , Mitsuhiro Wada , Yozo Oguri
发明人： Norihiko Moriwaki , Takahiko Kozaki , Takaaki Toyama , Mitsuhiro Wada , Yozo Oguri
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/153 , H04L49/1538 , H04L49/1576 , H04L49/255 , H04L49/3081 , H04L49/455 , H04L2012/565 , H04L2012/5681 , H04Q11/0478
摘要： An ATM switch that can be expanded to form a large scale ATM switch with minimal hardware additions. The ATM switch includes a plurality of ATM switch units arranged in parallel, a plurality of cell distributors arranged on the input side of the ATM switch units, and a plurality of cell assemblers arranged on the output side of the ATM switch units. Each of the cell distributors distributes ATM cells received from a plurality of incoming highways to a buffer memory having a plurality of queues corresponding to the output ports of the ATM switch units, namely destinations of the ATM cells, and stores the ATM cells to the queues in the buffer memory. Each cell distributor reads ATM cells having the same destination information, and outputs such ATM cells to respective ones of the ATM switch units in parallel. Each of the ATM switch units independently exchanges the received ATM cell in parallel with the other ATM switch units. Each of the cell assemblers multiplexes ATM cells received from the ATM switch units in a manner to preserve the time sequential order of the ATM cells, and outputs the ATM cells to one of a plurality of outgoing highways. A desired increase in the capacity of the ATM switch is implemented by adding an ATM switch unit between the cell distributors and the cell assemblers, thereby allowing for an increase in hardware in proportion to the desired increase in capacity.
摘要翻译：一个ATM交换机，可以扩展，形成一个大型ATM交换机，最少的硬件添加。 ATM交换机包括并行布置的多个ATM交换单元，布置在ATM交换单元的输入侧的多个单元分配器，以及布置在ATM交换单元的输出侧的多个单元汇编器。每个小区分配器将从多个入站高速公路接收的ATM信元分配到具有对应于ATM交换单元的输出端口的多个队列的缓冲存储器，即ATM信元的目的地，并将ATM信元存储到队列在缓冲存储器中。每个单元分配器读取具有相同目的地信息的ATM信元，并且将这些ATM信元并行地输出到相应的ATM交换单元。每个ATM交换单元与其他ATM交换单元并行地独立地交换所接收的ATM信元。每个小区装配器以保持ATM信元的时间顺序的方式复用从ATM交换机单元接收的ATM信元，并将ATM信元输出到多个输出高速公路中的一个。通过在单元分配器和单元组装器之间添加ATM交换单元来实现ATM交换机的容量的期望的增加，从而允许与期望的容量增加成比例地增加硬件。

4. 发明授权

US07023799B2 Leaky bucket type traffic shaper and bandwidth controller 失效
标题翻译：漏斗式流量整形器和带宽控制器
公开(公告)号：US07023799B2
公开(公告)日：2006-04-04
申请号：US10079583
申请日：2002-02-22
申请人： Masayuki Takase , Norihiko Moriwaki , Mitsuhiro Wada , Hiroaki Kasahara , Takahiko Kozaki
发明人： Masayuki Takase , Norihiko Moriwaki , Mitsuhiro Wada , Hiroaki Kasahara , Takahiko Kozaki
IPC分类号： H04L12/56
CPC分类号： H04L12/5602 , H04L47/22
摘要： A traffic shaper comprises a bandwidth controller 40 having a plurality of leaky bucket units 41-1 to 41-n prepared in correspondence with buffer memories 20-1 to 20-n, and an output queue designation unit 43 for specifying a buffer memory from which a packet is to be read out. Each of the leaky bucket units 41 has a level counter 416 for decrementing the count value at a predetermined rate, and a level increaser 411 to 417 for increasing the count value of the level counter by a value proportional to the product of the length of a transmitted packet and a unitary increment value which is variable depend on the current count value of the level counter.
摘要翻译：流量整形器包括具有对应于缓冲存储器20-1至20-n准备的多个泄漏桶单元41-1至41-n的带宽控制器40以及用于指定缓冲存储器的输出队列指定单元43，要读出一个数据包。每个漏斗单元41具有用于以预定速率递减计数值的电平计数器416和用于将电平计数器的计数值增加与水平计数器的长度成比例的值的电平增加器411至417 发送数据包和可变的单位增量值取决于电平计数器的当前计数值。

5. 发明授权

US07023849B2 Packet switching apparatus, method of transmitting multicast packet at packet switching apparatus, and setup method of packet switching apparatus 失效
公开(公告)号：US07023849B2
公开(公告)日：2006-04-04
申请号：US09922748
申请日：2001-08-07
申请人： Norihiko Moriwaki , Takahiko Kozaki , Masami Takahashi
发明人： Norihiko Moriwaki , Takahiko Kozaki , Masami Takahashi
IPC分类号： H04J3/26 , H04L12/56
CPC分类号： H04L49/254 , H04L49/201 , H04L49/30 , H04L49/3009 , H04L49/552
摘要： In a packet switching apparatus capable of multicast, the length of a bitmap added to a multicast packet is made variable, depending on the number of line interface cards housed in the packet switching apparatus.

6. 发明授权

US06463066B2 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06463066B2
公开(公告)日：2002-10-08
申请号：US09797696
申请日：2001-03-05
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

7. 发明授权

US06185212B2 ATM cell processing apparatus 失效
标题翻译： ATM信元处理装置
公开(公告)号：US06185212B2
公开(公告)日：2001-02-06
申请号：US09056770
申请日：1998-04-08
申请人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
发明人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
IPC分类号： H04L1228
CPC分类号： H04L49/254 , H04L49/30 , H04L2012/5681
摘要： An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
摘要翻译：一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。结果，可以形成具有大容量的快速电池缓冲器。本单元缓冲器也可以应用于FIFO等。

8. 发明授权

US06249524B1 Cell buffer memory for a large capacity and high throughput ATM switch 失效
标题翻译：用于大容量和高吞吐量ATM交换机的单元缓冲存储器
公开(公告)号：US06249524B1
公开(公告)日：2001-06-19
申请号：US09044171
申请日：1998-03-19
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

9. 发明授权

US08073420B2 Sensor net management method 有权
公开(公告)号：US08073420B2
公开(公告)日：2011-12-06
申请号：US12929655
申请日：2011-02-07
申请人： Norihiko Moriwaki
发明人： Norihiko Moriwaki
IPC分类号： H04B1/16 , G08B1/08
CPC分类号： H04L41/0893 , H04L41/0654 , H04L43/0817 , H04L43/12
摘要： There is provided a sensor node management method in which a user is unconscious of a service break even when a sensor mode has failed among a plurality of sensor nodes assuming intermittent operation. Moreover, it is possible to provide a flexible sensor node management method capable of freely modifying the observation grading (space, time) in accordance with a user's desire. A base station (30) for containing a plurality of intermittently operating sensor modes includes a sensor management table (4) for managing the sensor nodes, a group management table (5) for grouping a plurality of sensor nodes, and an operation timing control unit (3). The operation timing control unit (3) decides the operation interval and the relationship for starting each of the sensor nodes. Moreover, the base station and the sensor node have a counter value as a reference of the sensor node operation interval and the operation start phase, which are periodically synchronized.

10. 发明申请

US20110099054A1 HUMAN BEHAVIOR ANALYSIS SYSTEM 审中-公开
标题翻译：人类行为分析系统
公开(公告)号：US20110099054A1
公开(公告)日：2011-04-28
申请号：US12993551
申请日：2009-05-26
申请人： Norihiko Moriwaki , Kazuo Yano , Nobuo Sato , Satomi Tsuji , Koji Ara
发明人： Norihiko Moriwaki , Kazuo Yano , Nobuo Sato , Satomi Tsuji , Koji Ara
IPC分类号： G06Q10/00
CPC分类号： G06Q10/06 , G06Q10/063 , G06Q10/06395
摘要： In an organization dynamics analysis service using a sensor, organization dynamics information is understandably provided to a lot of members on a customer side without receiving private information such as an individual name from the customer. Therefore, a sensor data associated with an ID is received from the customer site, and organization analysis is performed on a service provider side, and then, an organization analysis data based on the ID is fed back to the customer site. When the customer browses the organization analysis data, the ID is converted into the private information in a service gateway installed on the customer site in accordance with a conversion table for correspondence of the ID previously specified on the customer side and the private information (individual name), and is shown to the customer as the understandable information.
摘要翻译：在使用传感器的组织动态分析服务中，可以将客户端的许多成员可理解地提供组织动态信息，而无需接收客户的个人信息等私人信息。因此，从客户站点接收与ID相关联的传感器数据，并且在服务提供方进行组织分析，然后将基于ID的组织分析数据反馈给客户站点。当客户浏览组织分析数据时，根据客户端先前指定的ID的对应关系的转换表和私人信息（个人名称）将ID转换成安装在客户站点上的服务网关中的私人信息），并向客户显示为可理解的信息。

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