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1. 再颁专利

USRE34583E Method of forming a configuration of interconnections on a semiconductor device having a high integration density 失效
标题翻译：在具有高积分密度的半导体器件上形成互连结构的方法
公开(公告)号：USRE34583E
公开(公告)日：1994-04-12
申请号：US880860
申请日：1992-05-11
申请人： Malcolm K. Grief , Trung T. Doan , Hendrikus J. W. van Houtum , Josephus M. F. G. van Laarhoven
发明人： Malcolm K. Grief , Trung T. Doan , Hendrikus J. W. van Houtum , Josephus M. F. G. van Laarhoven
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/76877
摘要： A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the islating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.
摘要翻译：一种方法，其特征在于，通过位于隔离层（12）的接触开口（16c）中的导电接触柱（18a），通过由半导体衬底（10）承载的有源区（11）获得接触，），然后形成互连（22）的金属构造，以与导电触头柱（18a）建立导电连接。隔离层（13）设置在隔离层（12）和导电层（18）之间，可以相对于隔离层（12）选择性地去除。因此，绝缘层（12）保持其原始平坦度，并且导电触头柱（18a）具有超过隔离层（12）的水平面（21）的上部水平（20），因此有利于这些触头柱之间的接触（18a）和互连（22）的金属构造。应用于具有高集成密度的微电路。

2. 发明授权

US5001079A Method of manufacturing a semiconductor device by forming insulating side walls with voids below overhangs 失效
标题翻译：通过形成具有低于突出端的空隙的绝缘侧壁来制造半导体器件的方法
公开(公告)号：US5001079A
公开(公告)日：1991-03-19
申请号：US368751
申请日：1989-06-20
申请人： Josephus M. F. G. Van Laarhoven , Wilhelmus F. M. Gootzen , Michael F. B. Bellersen , Trung T. Doan
发明人： Josephus M. F. G. Van Laarhoven , Wilhelmus F. M. Gootzen , Michael F. B. Bellersen , Trung T. Doan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/52
CPC分类号： H01L21/32136 , H01L21/76804 , H01L21/76885 , Y10S438/945
摘要： Spaced-apart regions (2) each having top (2a) and side walls (2b) meeting at an edge (20) are defined on a surface (1a) of a substructure (1) forming part of the device. A layer (3) of insulating material is provided over the surface (1a) and regions (2), so that the insulating material is provided preferentially at the edges (20) of the regions (2) to form adjacent the edges (20) portions (31) of the insulating material which overhang the underlying insulating material (32) provided on the surface (1a) and define a void therein. The insulating material layer (3) is then etched anisotropically to expose the top walls (2a). During the anisotropic etching the overhanging portions (31) initially mask the underlying insulating material provided on the surface (1a) so that the etching of the underlying insulating material is controlled by the etching away of the overhanging portions (31) and when the top walls (2 a) are exposed relatively gently sloping spacers or portions (30) of the insulating material remain on the side walls (2b). A further insulating material layer (4) may then be provided over the structure.

3. 发明授权

US4936950A Method of forming a configuration of interconnections on a semiconductor device having a high integration density 失效
标题翻译：在具有高积分密度的半导体器件上形成互连结构的方法
公开(公告)号：US4936950A
公开(公告)日：1990-06-26
申请号：US339029
申请日：1989-04-14
申请人： Trung T. Doan , Leendert De Bruin , Malcolm K. Grief , Harald Godon
发明人： Trung T. Doan , Leendert De Bruin , Malcolm K. Grief , Harald Godon
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76877
摘要： A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the isolating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.
摘要翻译：一种方法，其特征在于，通过位于隔离层（12）的接触开口（16c）中的导电接触柱（18a），通过由半导体衬底（10）承载的有源区（11）获得接触，），然后形成互连（22）的金属构造，以与导电触头柱（18a）建立导电连接。隔离层（13）设置在隔离层（12）和导电层（18）之间，可以相对于隔离层（12）选择性去除。因此，绝缘层（12）保持其原始平坦度，并且导电触头柱（18a）具有超过隔离层（12）的水平面（21）的上部水平（20），因此有利于这些触头柱之间的接触（18a）和互连（22）的金属构造。应用于具有高集成密度的微电路。

4. 发明授权

US08384192B2 Methods for forming small-scale capacitor structures 有权
标题翻译：形成小型电容器结构的方法
公开(公告)号：US08384192B2
公开(公告)日：2013-02-26
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

5. 发明授权

US08124491B2 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US08124491B2
公开(公告)日：2012-02-28
申请号：US12547197
申请日：2009-08-25
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

6. 发明申请

US20110284866A1 LIGHT-EMITTING DIODE (LED) STRUCTURE HAVING A WAVELENGTH-CONVERTING LAYER AND METHOD OF PRODUCING 审中-公开
标题翻译：具有波长转换层的发光二极管（LED）结构及其制造方法
公开(公告)号：US20110284866A1
公开(公告)日：2011-11-24
申请号：US13191235
申请日：2011-07-26
申请人： CHUONG A. TRAN , Trung T. Doan , Jui-Kang Yen , Yung-Wei Chen
发明人： CHUONG A. TRAN , Trung T. Doan , Jui-Kang Yen , Yung-Wei Chen
IPC分类号： H01L33/42 , H01L33/40 , H01L33/50
CPC分类号： H01L33/0079 , H01L33/22 , H01L33/44 , H01L33/508 , H01L33/641 , H01L2224/48247 , H01L2224/48257 , H01L2224/8592 , H01L2924/181 , H01L2924/00012
摘要： A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.
摘要翻译：提供了具有用于产生均匀的白光的基本上保形的波长转换层的发光二极管（LED）装置以及在晶片和各个晶片级上制造所述LED的方法。 LED装置包括金属基板，耦合到金属基板的p型半导体，耦合到p型半导体的有源区，耦合到有源区的n型半导体以及耦合到n型半导体的波长转换层型半导体。

7. 发明授权

US07935950B2 Controllable ovonic phase-change semiconductor memory device and methods of programming the same 有权
标题翻译：可控的卵子相变半导体存储器件及其编程方法
公开(公告)号：US07935950B2
公开(公告)日：2011-05-03
申请号：US11833034
申请日：2007-08-02
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L47/00 , H01L29/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。这种存储器件包括包括非平行侧壁的下电极。绝缘材料覆盖下电极，使得下电极的上表面露出。在一个实施例中，绝缘材料和下电极可以具有共面上表面。在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。硫族化物材料和上电极形成在下电极的上表面上。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

8. 发明授权

US07771537B2 Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition 有权
标题翻译：用于在微特征工件加工（例如CVD沉积）期间控制温度的方法和系统
公开(公告)号：US07771537B2
公开(公告)日：2010-08-10
申请号：US11418337
申请日：2006-05-04
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

9. 发明授权

US07656012B2 Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices away from one another 有权
标题翻译：用于半导体晶片处理的用于横向移位各个半导体器件彼此远离的装置
公开(公告)号：US07656012B2
公开(公告)日：2010-02-02
申请号：US11409350
申请日：2006-04-21
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/1191 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01032 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/29099 , H01L2924/00 , H01L2224/05099
摘要： A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.
摘要翻译：提供了在其基本上所有表面上具有钝化层以形成气密密封封装的芯片级或晶圆级封装。封装可以通过在半导体晶片的无源或背面上设置第一钝化层来形成。半导体晶片可以附接到柔性膜并且例如通过晶片锯切割，以分离半导体器件。一旦切割，柔性膜可以被拉伸，以使各个半导体器件彼此横向移位并且基本上暴露其侧边缘。一旦半导体器件的侧边缘被暴露，就可以在器件的侧边缘和有源表面上形成钝化层。可以去除每个半导体器件的有源表面上的钝化层的一部分，以便暴露在其下形成的导电元件。

10. 发明授权

US07625694B2 Selective provision of a diblock copolymer material 有权
标题翻译：选择性提供二嵌段共聚物材料
公开(公告)号：US07625694B2
公开(公告)日：2009-12-01
申请号：US10840535
申请日：2004-05-06
申请人： Eugene P. Marsh , Daryl C. New , Trung T. Doan
发明人： Eugene P. Marsh , Daryl C. New , Trung T. Doan
IPC分类号： B05D1/36 , G03F1/00
CPC分类号： H01L21/0274 , G03F7/039 , H01L21/312
摘要： Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an embodiment, the DBCP film is deposited on the circuit layer to be etched. Then the DCBP film is confined to define an area of interest in the DCBP film in which hexagonal domains will eventually be formed. Such confinement can constitute masking and exposing the DCBP film using photolithographic techniques. Such masking preferably incorporates knowledge of the domain spacing and/or grain size of the to-be-formed domains in the area of interest to ensure that a predictable number and/or orientation of the domains will result in the area of interest, although this is not strictly necessary in all useful embodiments. Domains are then formed in the area of interest in the DBCP film which comprises a hexagonal array of cylindrical domains in a matrix. The film is then treated (e.g., with osmium or ozone) to render either the domains or the matrix susceptible to removal, while the other component is then used as a mask to etch either dots or holes in the underlying circuit layer.
摘要翻译：本文公开了使用二嵌段共聚物（DBCP）膜作为蚀刻掩模在集成电路层中形成小点或孔的技术。在一个实施例中，DBCP膜沉积在待蚀刻的电路层上。然后将DCBP膜限制在DCBP膜中限定最终将形成六方结构域的感兴趣区域。这种约束可以使用光刻技术构成掩蔽和暴露DCBP膜。这种掩蔽优选地结合了感兴趣区域中待形成区域的结构域间隔和/或晶粒尺寸的知识，以确保域的可预测数量和/或取向将导致感兴趣的区域，尽管这在所有有用的实施例中并不是绝对必要的。然后在DBCP膜中的感兴趣区域中形成畴，其包括在矩阵中的圆柱形域的六边形阵列。然后将膜处理（例如，用锇或臭氧）以使得区域或基质易于除去，而另一种组分然后用作掩模来蚀刻底层电路层中的任何点或孔。

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