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1. 发明授权

US5136362A Electrical contact with diffusion barrier 失效
标题翻译：与扩散屏障电接触
公开(公告)号：US5136362A
公开(公告)日：1992-08-04
申请号：US618490
申请日：1990-11-27
申请人： Malcolm K. Grief , Trung Doan
发明人： Malcolm K. Grief , Trung Doan
IPC分类号： H01L21/768 , H01L23/485 , H01L29/45
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L29/45 , H01L2924/0002
摘要： A device is provided by forming a diffusion barrier at the interface between a metalized contact and the surface of a semiconductor substrate. A three-layer sandwich is formed over the contact region and then annealed in free nitrogen. The sandwich is made of a titanium nitride layer interposed between layers of titanium. During the anneal, material from the titanium layer adjacent to the substrate migrates thereinto to produce a highly conductive diffusion region of titanium silicide. Concurrently during the anneal the other layer of titanium, which is exposed to the nitrogen atmosphere, is converted into a backing layer of titanium nitride which enhances the barrier effect of the titanium nitride layer at the center of the sandwich structure. The conversion of titanium to titanium nitride causes a physical expansion in the layer involved. This serves to enhance the thickness of the barrier layer at all locations, but of particular significance at the corners of the contact well. A diffusion region of controlled depth and the deposition of minimal amounts of titanium remote from the contact side itself are advantageous results of the disclosed process.
摘要翻译：通过在金属化接触和半导体衬底的表面之间的界面处形成扩散阻挡层来提供器件。在接触区域上形成三层夹层，然后在游离氮中退火。夹层由夹在钛层之间的氮化钛层制成。在退火期间，与邻近衬底的钛层的材料迁移到其中以产生钛硅化物的高导电性扩散区。同时在退火过程中，暴露于氮气氛下的另一层钛转化为氮化钛背衬层，这增强了氮化钛层在夹层结构中心的阻挡作用。钛转化为氮化钛会导致所涉层的物理膨胀。这用于增强所有位置处的阻挡层的厚度，但在接触孔的角部具有特别的意义。受控深度的扩散区域和远离接触侧本身的最小量钛的沉积是所公开的方法的有利结果。

2. 再颁专利

USRE34583E Method of forming a configuration of interconnections on a semiconductor device having a high integration density 失效
标题翻译：在具有高积分密度的半导体器件上形成互连结构的方法
公开(公告)号：USRE34583E
公开(公告)日：1994-04-12
申请号：US880860
申请日：1992-05-11
申请人： Malcolm K. Grief , Trung T. Doan , Hendrikus J. W. van Houtum , Josephus M. F. G. van Laarhoven
发明人： Malcolm K. Grief , Trung T. Doan , Hendrikus J. W. van Houtum , Josephus M. F. G. van Laarhoven
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/76877
摘要： A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the islating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.
摘要翻译：一种方法，其特征在于，通过位于隔离层（12）的接触开口（16c）中的导电接触柱（18a），通过由半导体衬底（10）承载的有源区（11）获得接触，），然后形成互连（22）的金属构造，以与导电触头柱（18a）建立导电连接。隔离层（13）设置在隔离层（12）和导电层（18）之间，可以相对于隔离层（12）选择性地去除。因此，绝缘层（12）保持其原始平坦度，并且导电触头柱（18a）具有超过隔离层（12）的水平面（21）的上部水平（20），因此有利于这些触头柱之间的接触（18a）和互连（22）的金属构造。应用于具有高集成密度的微电路。

3. 发明授权

US06555466B1 Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers 失效
标题翻译：半导体晶圆上镶嵌结构的两步化学机械平面化
公开(公告)号：US06555466B1
公开(公告)日：2003-04-29
申请号：US09280767
申请日：1999-03-29
申请人： Thomas Laursen , Malcolm K. Grief , Krishna P. Murella , Sanjay Basak
发明人： Thomas Laursen , Malcolm K. Grief , Krishna P. Murella , Sanjay Basak
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/31053 , H01L21/3212 , H01L21/76819
摘要： A method of improving planarity of semiconductor wafer surfaces containing damascene and dual-damascene circuitry using chemical-mechanical polishing techniques. The method includes using a first polishing step to substantially remove excess surface metal up to a detected end point. After rinsing, a second step of chemical-mechanical polishing is applied, using a second slurry that has a higher selectivity for dielectric than metal, preferably from 1.8 to 4 or more times greater. The second step of polishing, in accordance with the invention, has been found to substantially eliminate dishing and improve planarity.
摘要翻译：使用化学机械抛光技术改善包含镶嵌和双镶嵌电路的半导体晶片表面的平面性的方法。该方法包括使用第一抛光步骤将基本上除去多余的表面金属直到检测到的终点。冲洗后，使用具有比金属更高的电介质选择性的第二浆料，优选为1.8至4倍或更多倍的化学机械抛光的第二步骤。已经发现根据本发明的抛光的第二步骤基本上消除了凹陷并改善了平面度。

4. 发明授权

US08666505B2 Wafer-scale package including power source 有权
标题翻译：晶圆级封装，包括电源
公开(公告)号：US08666505B2
公开(公告)日：2014-03-04
申请号：US13016253
申请日：2011-01-28
申请人： Richard J. O'Brien , John K. Day , Paul F. Gerrish , Michael F. Mattes , David A. Ruben , Malcolm K. Grief
发明人： Richard J. O'Brien , John K. Day , Paul F. Gerrish , Michael F. Mattes , David A. Ruben , Malcolm K. Grief
IPC分类号： A61N1/05
CPC分类号： H01L23/12 , A61B5/0031 , A61B5/01 , A61B5/03 , A61B5/11 , A61N1/37211 , A61N1/3758 , B81B2201/0214 , B81B2207/012 , B81C1/0023 , H01L23/58 , H01L25/0655 , H01L2223/6677 , H01L2224/16145 , H01L2224/16225 , H01L2924/1461 , H01L2924/15153 , H01L2924/15192 , H01L2924/15313 , H01L2924/16195 , H01L2924/16251 , H01L2924/19105 , H01L2924/00
摘要： A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material. The second substrate includes at least one of a second semiconductor material and a second insulating material. The second substrate is bonded to the first substrate such that the first and second substrates define an enclosed cavity between the first and second substrates. The control module is disposed within the enclosed cavity. The control module is configured to at least one of determine a physiological parameter of a patient and deliver electrical stimulation to the patient. The energy storage device is disposed within the cavity and is configured to supply power to the control module.
摘要翻译：医疗装置包括第一基板，第二基板，控制模块和能量存储装置。第一基板包括第一半导体材料和第一绝缘材料中的至少一个。第二基板包括第二半导体材料和第二绝缘材料中的至少一个。第二基板被结合到第一基板，使得第一和第二基板在第一和第二基板之间限定封闭的空腔。控制模块设置在封闭腔内。控制模块被配置为至少确定患者的生理参数并向患者传递电刺激中的至少一个。能量存储装置设置在空腔内并被配置为向控制模块供电。

5. 发明申请

US20120101540A1 WAFER-SCALE PACKAGE INCLUDING POWER SOURCE 有权
标题翻译：包括电源的WAFER-SCALE包装
公开(公告)号：US20120101540A1
公开(公告)日：2012-04-26
申请号：US13016253
申请日：2011-01-28
申请人： Richard J. O'Brien , John K. Day , Paul F. Gerrish , Michael F. Mattes , David A. Ruben , Malcolm K. Grief
发明人： Richard J. O'Brien , John K. Day , Paul F. Gerrish , Michael F. Mattes , David A. Ruben , Malcolm K. Grief
IPC分类号： A61N1/05 , H01L23/538 , H01L29/84 , H01L31/12
CPC分类号： H01L23/12 , A61B5/0031 , A61B5/01 , A61B5/03 , A61B5/11 , A61N1/37211 , A61N1/3758 , B81B2201/0214 , B81B2207/012 , B81C1/0023 , H01L23/58 , H01L25/0655 , H01L2223/6677 , H01L2224/16145 , H01L2224/16225 , H01L2924/1461 , H01L2924/15153 , H01L2924/15192 , H01L2924/15313 , H01L2924/16195 , H01L2924/16251 , H01L2924/19105 , H01L2924/00
摘要： A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material. The second substrate includes at least one of a second semiconductor material and a second insulating material. The second substrate is bonded to the first substrate such that the first and second substrates define an enclosed cavity between the first and second substrates. The control module is disposed within the enclosed cavity. The control module is configured to at least one of determine a physiological parameter of a patient and deliver electrical stimulation to the patient. The energy storage device is disposed within the cavity and is configured to supply power to the control module.
摘要翻译：医疗装置包括第一基板，第二基板，控制模块和能量存储装置。第一基板包括第一半导体材料和第一绝缘材料中的至少一个。第二基板包括第二半导体材料和第二绝缘材料中的至少一个。第二基板被结合到第一基板，使得第一和第二基板在第一和第二基板之间限定封闭的空腔。控制模块设置在封闭腔内。控制模块被配置为至少确定患者的生理参数并向患者传递电刺激中的至少一个。能量存储装置设置在空腔内并被配置为向控制模块供电。

6. 发明授权

US06387188B1 Pad conditioning for copper-based semiconductor wafers 有权
标题翻译：用于铜基半导体晶片的衬垫调节
公开(公告)号：US06387188B1
公开(公告)日：2002-05-14
申请号：US09261868
申请日：1999-03-03
申请人： Thomas Laursen , Malcolm K. Grief , Krishna P. Murella , Sanjay Basak
发明人： Thomas Laursen , Malcolm K. Grief , Krishna P. Murella , Sanjay Basak
IPC分类号： B08B304
CPC分类号： B24B53/017
摘要： A method of conditioning pads used in the polishing of semiconductor wafers containing copper circuitry. The method includes applying a treatment solution that contains a reactant for particulate copper-containing debris on the pad resulting from the copper circuitry. Preferably, the reactant is a carboxylic acid present in a concentration of from about 0.1 to about 10 weight percent in a solution. The pH of the solution may be adjusted to the range from about 1 to about 6 with a compatible base.
摘要翻译：一种用于抛光包含铜电路的半导体晶片的调节垫的方法。该方法包括在由铜电路产生的衬垫上施加含有颗粒状含铜碎屑的反应物的处理溶液。优选地，反应物是在溶液中以约0.1至约10重量％的浓度存在的羧酸。溶液的pH可以用相容的碱调节至约1至约6的范围。

7. 发明授权

US5738562A Apparatus and method for planar end-point detection during chemical-mechanical polishing 失效
标题翻译：化学机械抛光过程中平面端点检测的装置和方法
公开(公告)号：US5738562A
公开(公告)日：1998-04-14
申请号：US590541
申请日：1996-01-24
申请人： Trung Tri Doan , Gurtej Singh Sandhu , Malcolm K. Grief
发明人： Trung Tri Doan , Gurtej Singh Sandhu , Malcolm K. Grief
IPC分类号： B24B37/013 , B24B49/12 , B24B49/16
CPC分类号： B24B37/013 , B24B49/12
摘要： A chemical-mechanical polishing apparatus includes a slurry-wetted polishing pad attached to a substantially planar surface of a platen. A wafer carrier is positioned in close proximity to the platen, and it has a substantially planar surface to which one side of a semiconductor wafer is removably attachable so that an opposing side of the semiconductor wafer is disposed against the polishing pad. An actuator imparts a translational motion to the platen so that the polishing pad moves relative to and in polishing contact with the semiconductor wafer. A sensor detects a change in the imparted translational motion corresponding to a change in the coefficient of friction between the polishing pad and the opposing side of the semiconductor wafer indicative of a planar end point on the opposing side of the semiconductor wafer. The sensor preferably includes a laser and a laser detector using a laser reflection or laser interferometric method to detect the change in the imparted translational motion. Also, the apparatus preferably includes a controller coupled to the sensor and the actuator to adjust the actuator in response to the sensor detecting a change in the imparted translational motion.
摘要翻译：化学机械抛光装置包括附着在压板的基本平坦的表面上的浆液润湿的抛光垫。晶片载体被定位成靠近压板，并且其具有基本平坦的表面，半导体晶片的一侧可移除地附接到该表面，使得半导体晶片的相对侧抵靠抛光垫设置。致动器向平台施加平移运动，使得抛光垫相对于半导体晶片相对于其和与半导体晶片进行抛光接触而移动。传感器检测对应于抛光垫和半导体晶片的相反侧之间的摩擦系数的变化的赋予的平移运动的变化，其指示半导体晶片的相对侧上的平面终点。传感器优选地包括激光器和使用激光反射或激光干涉法的激光检测器来检测所赋予的平移运动的变化。此外，该装置优选地包括耦合到传感器和致动器的控制器，以响应于传感器来检测致动器的变化来调节致动器。

8. 发明授权

US4936950A Method of forming a configuration of interconnections on a semiconductor device having a high integration density 失效
标题翻译：在具有高积分密度的半导体器件上形成互连结构的方法
公开(公告)号：US4936950A
公开(公告)日：1990-06-26
申请号：US339029
申请日：1989-04-14
申请人： Trung T. Doan , Leendert De Bruin , Malcolm K. Grief , Harald Godon
发明人： Trung T. Doan , Leendert De Bruin , Malcolm K. Grief , Harald Godon
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76877
摘要： A method of the kind consisting in that a contact is obtained with an active zone (11) carried by a semiconductor substrate (10) by means of conductive contact studs (18a) located in the contact openings (16c) of an isolating layer (12) and in that then a metallic configuration of interconnections (22) is formed establishing the conductive connection with the conductive contact studs (18a). A separation layer (13) is provided between the isolating layer (12) and the conductive layer (18), which can be eliminated selectively with respect to the isolating layer (12). Thus, the isolating layer (12) retains its original flatness and the conductive contact studs (18a) have an upper level (20) exceeding slightly the level (21) of the isolating layer (12), thus favoring the contact between these contact studs (18a) and the metallic configuration of interconnections (22). Application in microcircuits having a high integration density.
摘要翻译：一种方法，其特征在于，通过位于隔离层（12）的接触开口（16c）中的导电接触柱（18a），通过由半导体衬底（10）承载的有源区（11）获得接触，），然后形成互连（22）的金属构造，以与导电触头柱（18a）建立导电连接。隔离层（13）设置在隔离层（12）和导电层（18）之间，可以相对于隔离层（12）选择性去除。因此，绝缘层（12）保持其原始平坦度，并且导电触头柱（18a）具有超过隔离层（12）的水平面（21）的上部水平（20），因此有利于这些触头柱之间的接触（18a）和互连（22）的金属构造。应用于具有高集成密度的微电路。

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