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1. 发明授权

US08338249B2 Semiconductor device and method for manufacturing the same having improved polarization reversal characteristic 有权
标题翻译：具有改善的极化反转特性的半导体装置及其制造方法
公开(公告)号：US08338249B2
公开(公告)日：2012-12-25
申请号：US12031960
申请日：2008-02-15
申请人： Makoto Takahashi , Mitsushi Fujiki , Kenkichi Suezawa , Wensheng Wang , Ko Nakamura
发明人： Makoto Takahashi , Mitsushi Fujiki , Kenkichi Suezawa , Wensheng Wang , Ko Nakamura
IPC分类号： H01L21/8234
CPC分类号： H01L27/0733 , G11C11/22 , H01L27/11507 , H01L28/55
摘要： A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成下电极，使用靶溅射下电极上的强电介质膜，根据累积的使用时间在含氧气氛中对铁电体膜进行热处理用于制造铁电体膜的目标，并且在铁电体膜上形成上电极。

2. 发明申请

US20070122917A1 Forming method of ferroelectric capacitor and manufacturing method of semiconductor device 审中-公开
标题翻译：铁电电容器的形成方法和半导体器件的制造方法
公开(公告)号：US20070122917A1
公开(公告)日：2007-05-31
申请号：US11407207
申请日：2006-04-20
申请人： Mitsushi Fujiki , Kenkichi Suezawa , Makoto Takahashi , Ko Nakamura , Wensheng Wang
发明人： Mitsushi Fujiki , Kenkichi Suezawa , Makoto Takahashi , Ko Nakamura , Wensheng Wang
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： Disclosed is a ferroelectric capacitor forming method of allowing a FeRAM to be stably mass-produced. In forming the ferroelectric capacitor for the FeRAM, a PZT layer is formed on a lower electrode layer by a sputtering method. Then, a first RTA treatment for crystallizing the PZT is performed in an environment controlled such that predetermined capacitor performance such as a data holding property can be obtained regardless of the amount of a target previously used (used hours) in the sputtering method. For example, the O2 gas flow rate is controlled in an appropriate range during the first RTA treatment. Thereafter, formation of an upper electrode layer or a second RTA treatment is performed. As a result, the ferroelectric capacitor having predetermined capacitor performance can be formed with high yield, so that the FeRAM can be stably mass-produced.
摘要翻译：公开了一种允许稳定批量生产FeRAM的铁电电容器形成方法。在形成FeRAM的铁电电容器时，通过溅射法在下电极层上形成PZT层。然后，在控制环境中进行用于结晶PZT的第一RTA处理，使得可以获得诸如数据保持特性的预定电容器性能，而与溅射方法中先前使用的目标量（使用时数）无关。例如，在第一次RTA处理期间将O 2气体流量控制在适当的范围内。此后，进行上电极层的形成或第二RTA处理。结果，可以以高产率形成具有预定电容器性能的铁电电容器，从而可以稳定地批量生产FeRAM。

3. 发明申请

US20100207178A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100207178A1
公开(公告)日：2010-08-19
申请号：US12031960
申请日：2008-02-15
申请人： Makoto TAKAHASHI , Mitsushi Fujiki , Kenkichi Suezawa , Wensheng Wang , Ko Nakamura
发明人： Makoto TAKAHASHI , Mitsushi Fujiki , Kenkichi Suezawa , Wensheng Wang , Ko Nakamura
IPC分类号： H01L27/07 , H01L21/8242
CPC分类号： H01L27/0733 , G11C11/22 , H01L27/11507 , H01L28/55
摘要： A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成下电极，使用靶溅射下电极上的强电介质膜，根据累积的使用时间在含氧气氛中对铁电体膜进行热处理用于制造铁电体膜的目标，并且在铁电体膜上形成上电极。

4. 发明授权

US06713808B2 Semiconductor capacitor with diffusion prevention layer 有权
标题翻译：具有扩散防护层的半导体电容器
公开(公告)号：US06713808B2
公开(公告)日：2004-03-30
申请号：US10115208
申请日：2002-04-04
申请人： Wensheng Wang , Mitsushi Fujiki , Ko Nakamura
发明人： Wensheng Wang , Mitsushi Fujiki , Ko Nakamura
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L27/10814 , H01L28/55
摘要： There is provided the capacitor which has the lower electrode having a structure in which the first conductive layer containing a first metal, the second conductive layer that is formed on the first conductive layer and made of the metal oxide of the second metal different from the first metal, and the third conductive layer that is formed on the second conductive layer and made of the third metal different from the first metal are formed sequentially; the dielectric layer formed on the lower electrode; and the upper electrode formed on the capacitor dielectric layer.
摘要翻译：提供了具有下电极的电容器，其中第一导电层包含第一金属，第二导电层形成在第一导电层上并且由与第一金属不同的第二金属的金属氧化物金属，并且形成在第二导电层上并且由与第一金属不同的第三金属制成的第三导电层依次形成; 形成在下电极上的电介质层; 并且形成在电容器电介质层上的上电极。

5. 发明授权

US06933156B2 Semiconductor capacitor with diffusion prevention layer 有权
标题翻译：具有扩散防护层的半导体电容器
公开(公告)号：US06933156B2
公开(公告)日：2005-08-23
申请号：US10764519
申请日：2004-01-27
申请人： Wensheng Wang , Mitsushi Fujiki , Ko Nakamura
发明人： Wensheng Wang , Mitsushi Fujiki , Ko Nakamura
IPC分类号： H01L23/52 , H01L21/02 , H01L21/3205 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L21/00 , H01L31/113
CPC分类号： H01L28/75 , H01L27/10814 , H01L28/55
摘要： A capacitor which has a lower electrode having a structure in which the first conductive layer containing a first metal, a second conductive layer that is formed on the first conductive layer and made of the metal oxide of the second metal different from the first metal, and a third conductive layer that is formed on the second conductive layer and made of a third metal different from the first metal. These layers are formed sequentially. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the capacitor dielectric layer.
摘要翻译：一种具有下电极的电容器，其具有第一导电层，其包含第一金属，第二导电层，形成在第一导电层上，并且由与第一金属不同的第二金属的金属氧化物制成，第三导电层，其形成在第二导电层上并且由不同于第一金属的第三金属制成。这些层顺序地形成。在下电极上形成介电层，在电容介电层上形成上电极。

6. 发明申请

US20050072998A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050072998A1
公开(公告)日：2005-04-07
申请号：US10860577
申请日：2004-06-04
申请人： Jirou Miura , Mitsushi Fujiki , Aki Dote , Tomohiro Takamatsu
发明人： Jirou Miura , Mitsushi Fujiki , Aki Dote , Tomohiro Takamatsu
IPC分类号： H01L27/105 , H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76802 , H01L21/76895 , H01L27/11507 , H01L28/40
摘要： An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
摘要翻译：形成覆盖铁电电容器的层间绝缘膜，并且通过层间绝缘膜形成各自到达电容器电极的接触孔。通过接触孔连接到电容器电极的布线进一步形成在层间绝缘膜的上方。接触孔的平面形状是正八边形，其四个角度为正方形的规则矩形，其相邻侧的长度彼此不同的八边形，圆形等。

7. 发明申请

US20070249065A1 Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20070249065A1
公开(公告)日：2007-10-25
申请号：US11510554
申请日：2006-08-28
申请人： Mitsushi Fujiki
发明人： Mitsushi Fujiki
IPC分类号： H01L21/00
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： After an interlayer insulating film and a lower side layer of a conductive film for a bottom electrode and the like are formed above a substrate, a Pt film of a thickness of 50 nm to 500 nm, for example, about 175 nm is formed on the lower side layer as an upper side layer of a conductive film for a bottom electrode by a DC magnetron sputtering method. As the lower side layer, for example, a Ti film is formed. A substrate temperature at a time of forming the upper side layer is set at 250° C. to 450° C., for example, at 350° C. By forming the upper side layer in such a substrate temperature, the upper side layer intense in orientation in a [222] direction is obtained. Therefore, orientation of a ferroelectric film which is formed directly thereon to a [111] direction also becomes extremely favorable.
摘要翻译：在衬底上方形成层间绝缘膜和底电极用导电膜的下侧层之后，形成厚度为50nm〜500nm，例如约175nm的Pt膜，作为用于底部电极的导电膜的上侧层的下侧层通过DC磁控溅射法。作为下侧层，例如可以形成Ti膜。在形成上侧层时的基板温度设定为250℃〜450℃，例如350℃。通过在这样的基板温度下形成上侧层，上侧层强烈获得沿[222]方向的取向。因此，直接形成在[111]方向上的铁电体膜的取向也变得非常有利。

8. 发明申请

US20060118847A1 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060118847A1
公开(公告)日：2006-06-08
申请号：US11093146
申请日：2005-03-30
申请人： Tomohiro Takamatsu , Mitsushi Fujiki
发明人： Tomohiro Takamatsu , Mitsushi Fujiki
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/11507 , H01L21/76816 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L27/11502 , H01L28/65
摘要： An upper electrode layer is processed into plural electrode shapes with lithography and subsequent dry etching to pattern plural upper electrodes, followed by conducting an RTA treatment at a treatment temperature of a value in a range from 400° C. to 1000° C. and at an oxygen flow volume of a value in a range from 0.1 L/min to 100 L/min and, subsequently, by conducting an annealing treatment at a treatment temperature of 650° C. in an oxygen atmosphere for 60 minutes.
摘要翻译：将上电极层通过光刻和随后的干蚀刻加工成多个电极形状以图案化多个上电极，然后在处理温度为400℃至1000℃的范围内进行RTA处理，然后在氧气流量为0.1L / min〜100L / min的范围，然后在氧气氛中在650℃的处理温度下进行退火处理60分钟。

9. 发明授权

US07518173B2 Semiconductor device having ferroelectric capacitor and its manufacture method 有权
标题翻译：具有铁电电容器的半导体器件及其制造方法
公开(公告)号：US07518173B2
公开(公告)日：2009-04-14
申请号：US11129490
申请日：2005-05-16
申请人： Yukinobu Hikosaka , Mitsushi Fujiki , Kazutoshi Izumi , Naoya Sashida , Aki Dote
发明人： Yukinobu Hikosaka , Mitsushi Fujiki , Kazutoshi Izumi , Naoya Sashida , Aki Dote
IPC分类号： H01L29/41 , H01L29/43
CPC分类号： H01L27/11507 , H01L21/76816 , H01L21/76832 , H01L21/7687 , H01L27/11502 , H01L28/57
摘要： A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.
摘要翻译：半导体器件包括：半导体衬底; 形成在所述半导体衬底中并且在所述绝缘栅极的两侧具有绝缘栅极和源极/漏极区域的MOS晶体管; 形成在半导体衬底上并具有下电极，铁电层和上电极的铁电电容器; 形成在上电极上并具有比上电极的厚度的一半或更薄的厚度的金属膜; 埋置铁电电容器和金属膜的层间绝缘膜; 通过层间绝缘膜形成的导电插塞，到达金属膜并且包括导电胶膜和钨体; 以及形成在层间绝缘膜上并连接到导电插塞的铝布线。解决了上电极接触附近的新问题，否则可能是通过在F电容器上采用W插头引起的。

10. 发明申请

US20060157762A1 Semiconductor device having ferroelectric capacitor and its manufacture method 有权
公开(公告)号：US20060157762A1
公开(公告)日：2006-07-20
申请号：US11129490
申请日：2005-05-16
申请人： Yukinobu Hikosaka , Mitsushi Fujiki , Kazutoshi Izumi , Naoya Sashida , Aki Dote
发明人： Yukinobu Hikosaka , Mitsushi Fujiki , Kazutoshi Izumi , Naoya Sashida , Aki Dote
IPC分类号： H01L29/94
CPC分类号： H01L27/11507 , H01L21/76816 , H01L21/76832 , H01L21/7687 , H01L27/11502 , H01L28/57
摘要： A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

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