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1. 发明授权

US07278085B1 Simple error-correction codes for data buffers 有权
标题翻译：数据缓冲区的简单纠错码
公开(公告)号：US07278085B1
公开(公告)日：2007-10-02
申请号：US10608320
申请日：2003-06-27
申请人： Lih-Jyh Weng , Bruce Buch
发明人： Lih-Jyh Weng , Bruce Buch
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1008 , G11C2029/0411 , G11C2207/104
摘要： A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits. The parity check bits are stored in the buffer memory along with the data. The stored data and parity check bits are read and the read data is used to regenerate the parity check bits. A result produced from the stored and regenerated parity check bits is usable to directly identify a location of an erroneous bit of the data in the buffer memory.
摘要翻译：提出了一种用于处理存储在存储器中的数据中出现的错误的方法和装置。要存储在缓冲存储器中的数据被应用于发生器矩阵以产生奇偶校验位。奇偶校验位与数据一起存储在缓冲存储器中。读取存储的数据和奇偶校验位，并且使用读取的数据来重新生成奇偶校验位。由存储和再生的奇偶校验位产生的结果可用于直接识别缓冲存储器中数据的错误位的位置。

2. 发明授权

US06581180B1 System and method for performing a Chien search using multiple Galois field elements 失效
公开(公告)号：US06581180B1
公开(公告)日：2003-06-17
申请号：US09527736
申请日：2000-03-17
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/158
摘要： A system for performing a Chien search simultaneously tests multiple elements of GF(2P) as possible roots of a degree-t error locator polynomial &sgr;(x) using a plurality of simplified multipliers that each simultaneously produce the corresponding terms of &sgr;(x). In one embodiment of the system, t−1 simplified multipliers over GF(2P) are used to simultaneously test as possible roots &agr;2, (&agr;2)2, (&agr;2)3 . . . (&agr;2)j. Each multiplier includes a plurality of adders that are set up in accordance with precomputed terms that are based on combinations of the weight-one elements of GF(2P). A summing circuit adds together the associated terms produced by the multipliers and produces j sums, which are then evaluated to test the j individual elements as possible roots. The coefficients of &sgr;(&agr;2)j are then fed back to the multipliers, and the multipliers test, during a next clock cycle, the elements &agr;2*(&agr;2)j, (&agr;2)2*(&agr;2)j . . . , (&agr;2)2j and so forth. Similar multipliers also test the odd powers of &agr; as roots of &sgr;′(x)=&sgr;(&agr;x). If P=mn the system may be implemented using a plurality of GF(2m) multipliers. The field GF(2m) is a subfield of GF(2P), and the elements of GF(2P) can each be represented by a combination of n elements of GF(2m). The error locator polynomial &sgr;(x) can thus be represented by a combination of n expressions &sgr;0(x), &sgr;2(x) . . . &sgr;n−1(x), each with coefficients that are elements of GF(2m). Each of the n expressions has 2m−1 coefficients for the terms x0, x1, x2 . . . x2m−1. Thus, n(2m−2) constant GF(2m) multipliers are used to test each element of GF(2P) as a possible root. The number of GF(2m) multipliers in the system is independent of the degree of the error locator polynomial, and each multiplier operates over a subfield of GF(2P). Accordingly, the system can simultaneously tests j elements using j sets of n(2m−2) constant multipliers over GF(2m).

3. 发明授权

US06226772B1 Pipelined combined system for producing error correction code symbols and error syndromes for large ECC redundancy 有权
标题翻译：流水线组合系统，用于产生用于大ECC冗余的纠错码符号和错误综合征
公开(公告)号：US06226772B1
公开(公告)日：2001-05-01
申请号：US09187144
申请日：1998-11-06
申请人： Lih-Jyh Weng , Diana Langer
发明人： Lih-Jyh Weng , Diana Langer
IPC分类号： H03M1300
CPC分类号： H03M13/1555 , H03M13/158
摘要： An n-stage pipelined combined encoder and syndrome generator system includes n stages that are essentially identical. Each of the stages includes two associated delay circuits, namely, a first delay circuit in a chain of feedback adders that operate as a feedback path during encoding, and a second delay circuit in a data input line. During encoding operations, the delay circuits in the feedback adder chain segment the chain of j feedback adders into n stages of j/n adders, and the delay circuits in the data input line delay the data symbols by the latencies associated with the respective stages. The delay circuits thus simultaneously provide to the various stages the corresponding data symbols and propagating sums. After the last data symbol is encoded, the ECC symbols are available after a time lag associated with the j/n adders in the last stage. During syndrome generation operations, the feedback adders are essentially decoupled from one another by AND gates that are included in the feedback path and switches in the data input line bypass the delay circuits, to avoid introducing latency into the syndrome generation operations.
摘要翻译： n级流水线组合编码器和综合征发生器系统包括基本相同的n个阶段。每个级包括两个相关联的延迟电路，即，在编码期间作为反馈路径工作的反馈加法器链中的第一延迟电路，以及数据输入线中的第二延迟电路。在编码操作期间，反馈加法器链中的延迟电路将j个反馈加法器链分段成j个加法器的n个级，并且数据输入行中的延迟电路通过与各个级相关联的延迟来延迟数据符号。因此，延迟电路同时向各个阶段提供对应的数据符号和传播和。在最后一个数据符号被编码之后，ECC符号在与最后阶段中的j / n加法器相关联的时滞之后可用。在校正子发生操作期间，反馈加法器基本上通过包括在反馈路径中的AND门和数据输入线中的开关绕过延迟电路彼此解耦，以避免将延迟引入到校正子生成操作中。

4. 发明授权

US5768296A ECC system supporting different-length Reed-Solomon codes whose generator polynomials have common roots 失效
标题翻译： ECC系统支持不同长度的里德 - 所罗门码，其生成多项式具有共同的根
公开(公告)号：US5768296A
公开(公告)日：1998-06-16
申请号：US761689
申请日：1996-12-06
申请人： Diana Langer , Michael Leis , Cecil Macgregor , Lih-Jyh Weng
发明人： Diana Langer , Michael Leis , Cecil Macgregor , Lih-Jyh Weng
IPC分类号： H03M13/15 , H03M13/35 , H03M13/00
CPC分类号： H03M13/6516 , H03M13/151 , H03M13/35
摘要： A Reed-Solomon error-correction coding (ECC) scheme selectively supports two different-length codes to optimize the trade-off between error performance and the amount of disk space required to store protection symbols. The encoder contains two sets of alpha multipliers; part of one set is multiplexed with the other depending on which code is being used. Also, a shift register within the encoder is selectively lengthened or shortened depending on the code. The code pair is selected so that the generator polynomial of the shorter code is a complete divisor of the generator polynomial of the longer code. Thus, one code is a sub-code of the other. Accordingly, the ECC system is able to use the same syndrome calculator for each code. The error-correction decoder uses those syndromes that correspond to the roots of the generator polynomial of the code being used.
摘要翻译： Reed-Solomon纠错编码（ECC）方案选择性地支持两个不同长度的代码来优化误差性能与存储保护符号所需的磁盘空间量之间的权衡。编码器包含两组α乘数; 根据正在使用的代码，一组的一部分与另一组复用。此外，根据代码，编码器内的移位寄存器被选择性地延长或缩短。选择代码对，使得较短代码的生成多项式是较长代码的生成多项式的完全除数。因此，一个代码是另一个的子代码。因此，ECC系统能够对每个代码使用相同的校正子计算器。纠错解码器使用与所使用代码的生成多项式的根相对应的那些校正子。

5. 发明授权

US5365382A Synchronization to different fields in a storage device 失效
标题翻译：同步到存储设备中的不同字段
公开(公告)号：US5365382A
公开(公告)日：1994-11-15
申请号：US064286
申请日：1993-05-18
申请人： Lih-Jyh Weng , Michael E. Kastner , Bruce Leshay
发明人： Lih-Jyh Weng , Michael E. Kastner , Bruce Leshay
IPC分类号： G11B20/14 , G11B27/30 , G11B5/09
CPC分类号： G11B20/1426 , G11B27/3027
摘要： A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.
摘要翻译：用于识别和同步到磁盘驱动器中的两个不同字段的方法和装置采用不同的同步或“同步”模式，以减少错误识别和伪识别字段的机会。已经发现两种非常不同的同步模式满足磁盘驱动器中使用的数据码的d = 1，k = 7游程长度限制。在操作期间，搜索一个同步模式以识别并同步到其相关联的字段，然后读取字段本身。然后对其他同步模式及其相关字段重复该过程。此外，在每个同步字符之前的前导码的相位被建立，使得找到同步字符所需的比较的数量减少。同步检测器对单元对进行操作，并且具有选择器来选择要搜索的同步模式。同步检测器还具有使其能够在磁盘单元流中找到前导码和直流擦除字段的特殊功能。

6. 发明授权

US5237574A Error-resilient information encoding 失效
标题翻译：错误恢复信息编码
公开(公告)号：US5237574A
公开(公告)日：1993-08-17
申请号：US808035
申请日：1991-12-11
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G11B20/18 , H03M13/29
CPC分类号： G11B20/1883 , G11B20/1813 , H03M13/29 , G11B2220/20
摘要： A method for determining whether particular information was used in encoding a codeword; the codeword is formed by encoding information as a first preliminary code sequence using a first code and then combining the first preliminary code sequence with a second preliminary code sequence generated using a second code; the particular information is encoded as a desired first preliminary code sequence in accordance with said first code; the desired first preliminary code sequence is then stripped from the codeword to derive a test sequence; the test sequence is decoded in accordance with the second code, and a determination is made, based on the decoding, whether the particular information was used in encoding the codeword. In another aspect, bad sector, servo correction, and sector address values are encoded for storage in a header associated with a sector of storage on a storage medium by encoding the address value with leading zero symbols in accordance with a code having a first rate, encoding the bad sector and servo correction values in a systematic code having a second rate, and combining these sequences to generate a codeword of the first code such that the bad sector and servo correction values appear explicitly in the codeword.
摘要翻译：一种用于确定在编码码字时是否使用特定信息的方法; 通过使用第一码将信息编码为第一初步码序列，然后将第一初步码序列与使用第二码产生的第二初步码序列组合来形成码字; 所述特定信息根据所述第一代码被编码为期望的第一初步代码序列; 然后从码字中去除期望的第一初步码序列以导出测试序列; 根据第二代码对测试序列进行解码，并且基于解码来确定特定信息是否用于编码码字。在另一方面，通过根据具有第一速率的代码对具有前导零符号的地址值进行编码，将坏扇区，伺服校正和扇区地址值编码为用于存储在与存储介质上的存储扇区相关联的报头中，对具有第二速率的系统代码中的坏扇区和伺服校正值进行编码，并组合这些序列以生成第一代码的码字，使得坏扇区和伺服校正值明显地出现在码字中。

7. 发明授权

US5136592A Error detection and correction system for long burst errors 失效
标题翻译：错误检测和纠正系统的长期错误
公开(公告)号：US5136592A
公开(公告)日：1992-08-04
申请号：US373323
申请日：1989-06-28
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , H03M13/15 , H04L1/00
CPC分类号： H03M13/15 , G11B20/1833
摘要： The invention is an error detection and correction system which encodes data twice, once for error detection by using a cyclic redundancy check (CRC) code with a generator polynomial, g(x) [in octal form]:g(x)=2413607036565172433223and a second time for error correction by using a Reed-Solomon error correction code. The system then uses the CRC code to check the data for errors. If errors are found the system uses the error location information supplied by the CRC code and the Reed-Solomon code to correct the errors.

8. 发明授权

US4914535A Synchronization for stored data 失效
标题翻译：存储数据同步
公开(公告)号：US4914535A
公开(公告)日：1990-04-03
申请号：US141204
申请日：1988-01-06
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G11B20/14 , G11B20/12 , G11B27/10 , G11B27/30
CPC分类号： G11B20/1252 , G11B27/3027 , G11B2220/20
摘要： The location of the sequence of data bits stored on a storage medium is identified by generating a predetermined synchronization bit sequence; storing on the storage medium a bit sequence corresponding to the predetermined synchronization sequence to indicate the location of the data bit sequence; deriving from the stored corresponding bit sequence on the storage medium a trial sequence; and determining whether the trial sequence corresponds to the predetermined synchronization sequence by determining the number of symbols in which the trial sequence differs from the predetermined synchronization sequence, each symbol comprising a plurality of bits, whereby the effect of clustered bit errors is reduced. The stored data bits are encoded from raw data bits in accordance with a code in which raw data symbols are encoded as data bit groups of at least two different lengths; a bit sequence corresponding to the synchronization sequence is stored on the medium as an indication of the location of the stored data bits; and the synchronization sequence comprises a sequence of raw data symbols which encode as stored encoded groups all of a single length, whereby error propagation is reduced.
摘要翻译：通过产生预定的同步比特序列来识别存储在存储介质上的数据比特序列的位置; 在所述存储介质上存储与所述预定同步序列相对应的比特序列，以指示所述数据比特序列的位置; 从存储介质上存储的对应比特序列导出试验序列; 以及通过确定所述试验序列与所述预定同步序列不同的符号的数量来确定所述试验序列是否对应于所述预定的同步序列，每个符号包括多个比特，从而降低了聚类比特错误的影响。存储的数据位根据原始数据符号被编码为至少两个不同长度的数据位组的代码从原始数据位进行编码; 对应于同步序列的位序列作为存储的数据位的位置的指示存储在介质上; 并且同步序列包括原始数据符号序列，其编码为所有单个长度的存储的编码组，由此减小了误差传播。

9. 发明授权

US4866716A Real-time BCH error correction code decoding mechanism 失效
标题翻译：实时BCH纠错码解码机制
公开(公告)号：US4866716A
公开(公告)日：1989-09-12
申请号：US146850
申请日：1988-01-22
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： The invention simultaneously calculates error locations and associated error values by solving the error locator polynomial equation re-written as:1=.delta..sub.even (x)+.delta..sub.odd (x)where .delta..sub.even (x) and .delta..sub.odd (x) are the even- and odd-power terms of the error locator polynomial. A first value of x, x.sub.a1, is simultaneously inserted into the expression .delta..sub.even (x) and .delta..sub.odd (x) and also into an error value polynomial .PHI.(x). Next, while the error locator equation is evaluated at the calculated values of .delta..sub.even (x.sub.a1) and .delta..sub.odd (x.sub.a1) to determine if x.sub.a1 is a solution, the now known values of the error evaluator polynomial .PHI.(x.sub.a1) and .delta..sub.odd (x.sub.a1) are substituted into an error value formula: ##EQU1## Thus as soon as an error location is found, the error value, v.sub.a1, associated with that location is also known. The error can then be quickly corrected. Next, these calculated terms are used to calculate similar expressions for a next value of x, x.sub.a2. If x.sub.a2 is a solution, the error value v.sub.a2 which was simultaneously calculated for x.sub.a2 is used to correct the error. If x.sub.a2 is not a solution, the calculated error value is ignored. The expression .delta..sub.odd (x), .delta..sub.even (x) and the polynominal .PHI.(x) are similarly evaluated for each of the remaining values of x.
摘要翻译：本发明通过解决重写的误差定位多项式方程式同时计算误差位置和相关误差值：1 = delta even（x）+ delta odd（x）其中delta even（x）和delta odd（x）是偶数 - 和错误定位多项式的奇数项。 x，xa1的第一个值被同时插入到表达式delta even（x）和delta odd（x）中，并且也被插入到错误值多项式PHI（x）中。接下来，当以计算的delta even（xa1）和delta odd（xa1）的值来评估误差定位器方程以确定xa1是否是解时，现在已知的误差评估多项式PHI（xa1）和delta odd（ xa1）被替换为误差值公式：因此，一旦发现错误位置，与该位置相关联的误差值va1也是已知的。然后可以快速更正错误。接下来，这些计算的项用于计算x，xa2的下一个值的相似表达式。如果xa2是解，则同时计算xa2的误差值va2用于校正误差。如果xa2不是解，则忽略计算出的误差值。对于x的剩余值中的每一个，类似地计算表达式delta odd（x），delta even（x）和多项式PHI（x）。

10. 发明授权

US4847705A Method and apparatus for encoding magnetic disk sector addresses 失效
标题翻译：用于编码磁盘扇区地址的方法和装置
公开(公告)号：US4847705A
公开(公告)日：1989-07-11
申请号：US70689
申请日：1987-07-07
申请人： Lih-Jyh Weng , Bernardo Rub
发明人： Lih-Jyh Weng , Bernardo Rub
IPC分类号： G06F3/06 , G11B20/12 , G11B20/18 , G11B27/10 , G11B27/30 , H03M13/15
CPC分类号： G11B27/105 , G11B20/1833 , G11B27/3027 , H03M13/15 , G11B2020/10916
摘要： The invention encodes magnetic disk sector addresses using a large distance, "d", Reed-Solomon code to produce code words which vary by at least "d" symbols for any two different encoded addresss. The result of the encoding is a set of redundancy symbols, which are usually associated with error correction. These symbols are appended to the address symbols to produce address code words. An address code word read from a disk can contain up to (d-1)/2 errors and still be identified as the correct sector address. To protect the encoded sector address from synchronization errors the address code words are further encoded by adding them to a coset leader to produce header code words. The header code words are then recorded in the address portions of the sectors. When a header code word is read from a sector, the coset leader is subtracted from the header code word to produce an address code word. The address code word is then compared with the address code word for the specified address. If there is a synchronization error, the comparison of the resulting address code word with the address code word for the specified address will result in a difference of more than (d-1)/2 symbols and the sector will not be treated as the specified address.
摘要翻译：本发明使用大距离“d”，Reed-Solomon码来编码磁盘扇区地址，以产生对于任何两个不同的编码地址至少“d”个符号而变化的码字。编码的结果是一组冗余符号，通常与纠错有关。这些符号被附加到地址符号以产生地址码字。从磁盘读取的地址码字可以包含高达（d-1）/ 2个错误，并且仍然被识别为正确的扇区地址。为了保护编码的扇区地址免于同步错误，地址码字通过将它们添加到陪集引导来产生标题码字进一步进行编码。然后，标题码字被记录在扇区的地址部分中。当从扇区读取标题码字时，从标题码字中减去陪集前导码以产生地址码字。然后将地址码字与指定地址的地址码字进行比较。如果存在同步错误，则所得到的地址代码字与指定地址的地址代码字的比较将导致大于（d-1）/ 2个符号的差异，并且扇区将不被视为指定的地址。

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