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1. 发明申请

US20110318895A1 FABRICATION METHOD OF TRENCHED POWER MOSFET 有权
标题翻译：激光功率MOSFET的制造方法
公开(公告)号：US20110318895A1
公开(公告)日：2011-12-29
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

2. 发明授权

US08426275B2 Fabrication method of trenched power MOSFET 有权
标题翻译：沟槽功率MOSFET的制造方法
公开(公告)号：US08426275B2
公开(公告)日：2013-04-23
申请号：US13225555
申请日：2011-09-06
申请人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
发明人： Kou-Way Tu , Hsiu-Wen Hsu , Yi-Yun Tsai , Yuan-Shun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
摘要翻译：提供了一种沟槽功率MOSFET的制造方法。在基板上形成具有第一开口的图案层。使用图案层作为掩模去除衬底的一部分，以在衬底中形成沟槽。沟槽的宽度扩大。栅极氧化层形成在沟槽的表面上。使用图案层作为掩模，去除沟槽底部上的栅极氧化物层的一部分，以在栅极氧化物层中形成第二个开口。扩展沟槽的宽度大于第二开口的宽度。在第二开口中形成厚的氧化物层。在厚氧化物层旁边形成重掺杂区域。在沟槽中形成栅极。形成围绕沟槽的主体层。源头在沟槽旁边形成。

3. 发明授权

US08890242B2 Closed cell trenched power semiconductor structure 有权
标题翻译：闭孔沟槽功率半导体结构
公开(公告)号：US08890242B2
公开(公告)日：2014-11-18
申请号：US13402945
申请日：2012-02-23
申请人： Yuan-Shun Chang , Kao-Way Tu , Yi-Yun Tsai
发明人： Yuan-Shun Chang , Kao-Way Tu , Yi-Yun Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.
摘要翻译：提供了一种闭孔沟槽功率半导体结构。闭孔沟槽功率半导体结构具有基板和单元。电池以阵列布置在基板上。每个细胞都有一个身体和一个沟槽的门。壕沟围绕着身体。沟槽门面对体的侧壁具有凹面。

4. 发明授权

US08916930B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08916930B2
公开(公告)日：2014-12-23
申请号：US13223603
申请日：2011-09-01
申请人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
发明人： Yuan-Shun Chang , Yi-Yun Tsai , Kao-Way Tu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/40 , H01L29/06 , H01L21/74 , H01L29/423 , H01L29/08
CPC分类号： H01L29/7809 , H01L21/74 , H01L29/0623 , H01L29/0653 , H01L29/0878 , H01L29/0882 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7812 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。该器件具有基极，至少包括栅极沟槽，多个第一重掺杂区域，体区域，源极掺杂区域，接触窗口，第二重掺杂区域和金属层的多个沟槽。沟槽形成在基部。第一重掺杂区域分别在沟槽下方并且与具有轻掺杂区域的相应沟槽的底部间隔开。体区域包围沟槽并且以预定距离远离第一重掺杂区域。源极掺杂区域位于体区的上部。接触窗口与基座的边缘相邻。第二重掺杂区域在由用于电连接第二重掺杂区域的金属层填充的接触窗口的下方。

5. 发明授权

US08735249B2 Trenched power semiconductor device and fabrication method thereof 有权
标题翻译：沟槽功率半导体器件及其制造方法
公开(公告)号：US08735249B2
公开(公告)日：2014-05-27
申请号：US13115951
申请日：2011-05-25
申请人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
发明人： Yi-Yun Tsai , Yuan-Shun Chang , Kao-Way Tu
IPC分类号： H01L21/326
CPC分类号： H01L29/7809 , H01L21/2253 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.
摘要翻译：提供了一种在轻掺杂衬底上的沟槽功率半导体器件。首先，在轻掺杂衬底上形成至少包括栅极沟槽和接触窗口的多个沟槽。然后，在沟槽的底部形成至少两个沟底重掺杂区域。然后通过使用热扩散工艺将这些沟底重掺杂区域扩展以彼此连接，从而形成导电路径。之后，栅极结构和阱形成在沟槽底部重掺杂区域上方，然后在接触窗口中形成导电结构，以将沟槽底部重掺杂区域电连接到电极。

6. 发明授权

US08421149B2 Trench power MOSFET structure with high switching speed and fabrication method thereof 有权
标题翻译：具有高切换速度的沟槽功率MOSFET结构及其制造方法
公开(公告)号：US08421149B2
公开(公告)日：2013-04-16
申请号：US13115981
申请日：2011-05-25
申请人： Yuan-Shun Chang , Kao-Way Tu
发明人： Yuan-Shun Chang , Kao-Way Tu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L27/088 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of trench power semiconductor structure with high switching speed is provided. An epitaxial layer with a first conductivity type is formed on a substrate. Then, gate structures are formed in the epitaxial layer. A shallow doped region with the first conductivity type is formed in the surface layer of the epitaxial layer. After that, a shielding structure is formed on the shallow doped region. Then, wells with a second conductivity type are formed in the epitaxial layer by using the shielding structure as an implantation mask. Finally, a source doped region with the first conductivity type is formed on the surface of the well. The doping concentration of the shallow doped layer is smaller than that of the source doped region and the well. The doping concentration of the shallow doped layer is larger than that of the epitaxial layer.
摘要翻译：提供了具有高切换速度的沟槽功率半导体结构的制造方法。在衬底上形成具有第一导电类型的外延层。然后，在外延层中形成栅极结构。在外延层的表面层中形成具有第一导电类型的浅掺杂区域。之后，在浅掺杂区域上形成屏蔽结构。然后，通过使用屏蔽结构作为注入掩模，在外延层中形成具有第二导电类型的阱。最后，在阱的表面上形成具有第一导电类型的源极掺杂区域。浅掺杂层的掺杂浓度小于源掺杂区和阱的掺杂浓度。浅掺杂层的掺杂浓度大于外延层的掺杂浓度。

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