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1. 发明授权

US6114247A Polishing cloth for use in a CMP process and a surface treatment thereof 失效
标题翻译：用于CMP工艺的抛光布及其表面处理
公开(公告)号：US6114247A
公开(公告)日：2000-09-05
申请号：US884549
申请日：1997-06-27
申请人： Ko Nakamura , Sadahiro Kishii , Yoshihiro Arimoto
发明人： Ko Nakamura , Sadahiro Kishii , Yoshihiro Arimoto
IPC分类号： B24B53/017 , B24D11/00 , B24D13/12 , C09G1/02 , H01L21/02 , H01L21/304 , H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： B24B53/013 , B24B37/044 , B24B53/017 , C09G1/02 , H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A method of fabricating a semiconductor device includes a step of polishing a surface of a substrate by a chemical mechanical polishing process conducted on a polishing cloth by a slurry. The polishing is conducted so that projections having a height of about 30 .mu.m or less are formed on the polishing cloth with an interval of about 55 .mu.m or less as a result of the polishing.
摘要翻译：制造半导体器件的方法包括通过在抛光布上通过浆料进行的化学机械抛光工艺来抛光衬底的表面的步骤。进行研磨，由此抛光的结果，在研磨布上以约55μm以下的间隔形成高度约30μm以下的凸起。

2. 发明授权

US6159858A Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry 失效
标题翻译：含有锰氧化物的浆料和使用这种浆料的半导体器件的制造方法
公开(公告)号：US6159858A
公开(公告)日：2000-12-12
申请号：US884165
申请日：1997-06-27
申请人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
发明人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
IPC分类号： C03C19/00 , C09G1/02 , C09K3/14 , C09K13/04 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： C09G1/02 , C03C19/00 , C09K3/1409 , C09K3/1463 , C09K3/1472 , C09K13/04 , H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

3. 发明授权

US5877089A Slurry containing manganese oxide 失效
标题翻译：含有氧化锰的浆料
公开(公告)号：US5877089A
公开(公告)日：1999-03-02
申请号：US14246
申请日：1998-01-27
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

4. 发明授权

US5763325A Fabrication process of a semiconductor device using a slurry containing manganese oxide 失效
标题翻译：使用含有氧化锰的浆料的半导体器件的制造方法
公开(公告)号：US5763325A
公开(公告)日：1998-06-09
申请号：US674507
申请日：1996-07-02
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

5. 发明授权

US5562529A Apparatus and method for uniformly polishing a wafer 失效
标题翻译：用于均匀抛光晶片的装置和方法
公开(公告)号：US5562529A
公开(公告)日：1996-10-08
申请号：US131949
申请日：1993-10-08
申请人： Sadahiro Kishii , Yoshihiro Arimoto , Hiroshi Horie , Fumitoshi Sugimoto
发明人： Sadahiro Kishii , Yoshihiro Arimoto , Hiroshi Horie , Fumitoshi Sugimoto
IPC分类号： B24B37/013 , B24B49/10 , B24B1/00 , B24B7/16
CPC分类号： B24B37/013 , B24B49/10 , Y10S451/908
摘要： An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.
摘要翻译：一种用于抛光半导体晶片的装置和方法。抛光机包括具有导电膜的支撑板和形成在支撑板的导电膜上的抛光布。抛光布具有多个开口以露出导电膜。晶片保持器具有导电晶片保持表面，以保持具有电流检测图案的半导体晶片和覆盖当前检测图案的绝缘膜。研磨浆料供给装置将包含离子的研磨浆料供给到研磨布或半导体晶片。连接到支撑板和晶片保持器的电流检测装置检测通过导电晶片保持表面流过支撑板和晶片保持器的电流的大小，由晶片保持器保持的半导体晶片，当前的检测模式的半导体晶片，填充在抛光布的开口中的抛光浆料和导电膜。

6. 发明授权

US5624300A Apparatus and method for uniformly polishing a wafer 失效
标题翻译：用于均匀抛光晶片的装置和方法
公开(公告)号：US5624300A
公开(公告)日：1997-04-29
申请号：US676663
申请日：1996-07-10
申请人： Sadahiro Kishii , Yoshihiro Arimoto
发明人： Sadahiro Kishii , Yoshihiro Arimoto
IPC分类号： B24B37/013 , B24B49/10 , B24B1/00 , B24B7/16
CPC分类号： B24B37/013 , B24B49/10 , Y10S451/908
摘要： For providing a method for polishing in which it is possible to polish a substance uniformly over a whole surface of a wafer without observing the polished surface of the wafer halfway through polishing, a wafer with current detective patterns formed of conductors directly contacted with a semiconductor substrate, and an insulating film covering the current detective patterns is held by a wafer holder with conductivity, and the insulating film is polished by a polisher in which a supporting plate with conductivity is exposed in openings through a polishing cloth while supplying a polishing slurry containing ions.
摘要翻译：为了提供抛光方法，其中可以在晶片的整个表面上均匀地抛光物质，而不通过抛光中途观察晶片的抛光表面，具有由与半导体基板直接接触的导体形成的电流检测图案的晶片并且覆盖电流检测图案的绝缘膜由具有导电性的晶片保持器保持，并且绝缘膜由抛光机抛光，其中通过抛光布将具有导电性的支撑板暴露在开口中，同时提供含有离子的抛光浆料。

7. 发明授权

US5904609A Polishing apparatus and polishing method 失效
标题翻译：抛光设备和抛光方法
公开(公告)号：US5904609A
公开(公告)日：1999-05-18
申请号：US637433
申请日：1996-04-25
申请人： Atsushi Fukuroda , Yoshihiro Arimoto , Ko Nakamura
发明人： Atsushi Fukuroda , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： B24B37/04 , G05B19/416 , B24B49/00
CPC分类号： B24B37/005 , G05B19/4163 , G05B2219/45199 , G05B2219/45232 , G05B2219/49085
摘要： A polishing apparatus comprises a first surface plate for supporting a polishing object, a driving mechanism for rotating the first surface plate, a second surface plate arranged so as to oppose to the first surface plate, an abrasive cloth stuck to the second surface plate, a vibration detector attached to the first surface plate or the second surface plate for detecting vibration in polishing, a controlling portion for controlling polishing operation of the first surface plate and the second surface plate, and signal analyzing unit for analyzing vibration intensity detected by the a vibration detector through frequency analysis, integrating the vibration intensity relative to time, and transmitting a polishing stop signal to stop polishing operation of the first surface plate and the second surface plate to the controlling portion when variation in a resultant integral value relative to time is less than a first reference value or when the resultant integral value is less than a second reference value.
摘要翻译：抛光装置包括用于支撑抛光对象的第一表面板，用于旋转第一表面板的驱动机构，与第一表面板相对布置的第二表面板，粘附到第二表面板的研磨布，振动检测器，附接到第一表面板或第二表面板，用于检测抛光中的振动;控制部分，用于控制第一表面板和第二表面板的抛光操作;以及信号分析单元，用于分析由振动检测的振动强度检测器通过频率分析，相对于时间的振动强度积分，并且当所得到的积分值相对于时间的变化小于时，传递抛光停止信号以停止将第一表面板和第二表面板的抛光操作到控制部分第一参考值或当所得积分值小于seco时 nd参考值。

8. 发明授权

US5413951A Composite semiconductor substrate and a fabrication process thereof 失效
标题翻译：复合半导体衬底及其制造工艺
公开(公告)号：US5413951A
公开(公告)日：1995-05-09
申请号：US19888
申请日：1993-02-19
申请人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
发明人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L27/01 , H01L29/04 , H01L21/302
CPC分类号： H01L21/76256 , H01L21/2007 , Y10S148/135
摘要： A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.
摘要翻译：一种制造SOI结构的方法，其包括将III-V族化合物半导体材料的单晶层与蓝宝石的单晶衬底接触的步骤，使得所述单晶层的主表面与相应的所述单晶基板的主表面，并且在升高温度的同时将单晶层和单晶基板彼此接合。

9. 发明授权

US5506433A Composite semiconductor substrate having a single crystal substrate and a single crystal layer formed thereon 失效
标题翻译：具有单晶基板和形成在其上的单晶层的复合半导体基板
公开(公告)号：US5506433A
公开(公告)日：1996-04-09
申请号：US277022
申请日：1994-08-24
申请人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
发明人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L27/01 , H01L29/04
CPC分类号： H01L21/76256 , H01L21/2007 , Y10S148/135
摘要： A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.
摘要翻译：一种绝缘体上硅（SOI）结构，其具有接触蓝宝石单晶衬底的III-V族化合物半导体材料的单晶层，使得单晶层的主表面与相应的主表面紧密接触的单晶衬底和单晶层，并且单晶衬底在升高温度的同时彼此接合。

10. 发明授权

US5037774A Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon 失效
标题翻译：利用多步沉积和非晶硅再结晶生产半导体器件的方法
公开(公告)号：US5037774A
公开(公告)日：1991-08-06
申请号：US73839
申请日：1987-07-15
申请人： Hideki Yamawaki , Yoshihiro Arimoto , Shigeo Kodama , Takafumi Kimura , Masaru Ihara
发明人： Hideki Yamawaki , Yoshihiro Arimoto , Shigeo Kodama , Takafumi Kimura , Masaru Ihara
IPC分类号： H01L27/12 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/86
CPC分类号： H01L21/324 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/0262 , Y10S148/017 , Y10S148/025 , Y10S148/15
摘要： Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.
摘要翻译：通过使用绝缘体上硅（SOI）技术制造半导体器件的工艺。 SOI结构的Si层包括Si的界面层和在其上形成的Si的缓冲层，由此可以有效地防止在Si层中形成堆垛层错。用钼酸盐溶液预处理下层绝缘材料，并在Si的缓冲层和上覆的有源Si层之间插入缓慢生长的单晶Si的附加层也有效地抑制堆垛层错。可以以良好的产量生产具有高质量的半导体器件。

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