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1. 发明授权

US07960784B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US07960784B2
公开(公告)日：2011-06-14
申请号：US12901243
申请日：2010-10-08
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L29/66
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

2. 发明申请

US20110037122A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20110037122A1
公开(公告)日：2011-02-17
申请号：US12901243
申请日：2010-10-08
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

3. 发明授权

US08093653B2 Trench metal oxide-semiconductor transistor and fabrication method thereof 有权
标题翻译：沟槽金属氧化物半导体晶体管及其制造方法
公开(公告)号：US08093653B2
公开(公告)日：2012-01-10
申请号：US12243406
申请日：2008-10-01
申请人： Kao-Way Tu , Cheng-Hui Tung , Hsiao-Wei Tsai
发明人： Kao-Way Tu , Cheng-Hui Tung , Hsiao-Wei Tsai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of a trench metal oxide-semiconductor (MOS) transistor is provided. After the gate trenches are formed in the epitaxial layer, impurities of a first conductive type are implanted into the epitaxial layer by using a blanket implantation process. A polysilicon pattern filling the gate trenches and covering a predetermined range of epitaxial layer surrounding the gate trenches is formed on the epitaxial layer. Impurities of a second conductive type are implanted through the polysilicon pattern into the epitaxial layer to form a well. Impurities of the first conductive type are implanted to form a plurality of first doping regions. A portion of the polysilicon layer above the upper surface of the epitaxial layer is removed by etching to form a plurality of polysilicon gates. Impurities in the first doping regions are driven in to form a plurality of source regions adjacent to the gate trenches.
摘要翻译：提供了一种沟槽金属氧化物半导体（MOS）晶体管的制造方法。在外延层中形成栅极沟槽之后，通过使用覆盖注入工艺将第一导电类型的杂质注入到外延层中。在外延层上形成填充栅极沟槽并覆盖围绕栅极沟槽的预定范围的外延层的多晶硅图案。第二导电类型的杂质通过多晶硅图案注入到外延层中以形成阱。第一导电类型的杂质被注入以形成多个第一掺杂区域。通过蚀刻去除外延层的上表面上方的多晶硅层的一部分，以形成多个多晶硅栅极。第一掺杂区域中的杂质被驱动以形成与栅极沟槽相邻的多个源极区域。

4. 发明授权

US07838343B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US07838343B2
公开(公告)日：2010-11-23
申请号：US12403660
申请日：2009-03-13
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L21/332
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

5. 发明申请

US20100025762A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20100025762A1
公开(公告)日：2010-02-04
申请号：US12403660
申请日：2009-03-13
申请人： Kao-Way Tu , Cheng-Hui Tung
发明人： Kao-Way Tu , Cheng-Hui Tung
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L27/088 , H01L29/0619 , H01L29/42372 , H01L29/66719 , H01L29/66727 , H01L29/7811
摘要： A semiconductor fabrication process according to the present invention defines an auxiliary structure with a plurality of spaces with a predetermined line-width in the oxide layer to prevent the conductive material in the spaces from being removed by etching or defined an auxiliary structure to rise the conductive structure so as to have the conductive structure being exposed by chemical mechanical polishing. Thus, the transmitting circuit can be defined without requiring an additional mask. Hence, the semiconductor fabrication process can reduce the number of required masks to lower the cost.
摘要翻译：根据本发明的半导体制造方法限定了在氧化物层中具有预定线宽的多个空间的辅助结构，以防止通过蚀刻或限定辅助结构来使空间中的导电材料被去除以使导电结构，使得导电结构通过化学机械抛光曝光。因此，可以限定发射电路而不需要额外的掩模。因此，半导体制造过程可以减少所需的掩模的数量以降低成本。

6. 发明授权

US08169019B2 Metal-oxide-semiconductor chip and fabrication method thereof 有权
标题翻译：金属氧化物半导体芯片及其制造方法
公开(公告)号：US08169019B2
公开(公告)日：2012-05-01
申请号：US12556715
申请日：2009-09-10
申请人： Kuo-Chang Tsen , Kao-Way Tu
发明人： Kuo-Chang Tsen , Kao-Way Tu
IPC分类号： H01L29/66
CPC分类号： H01L24/05 , H01L23/4824 , H01L24/03 , H01L24/06 , H01L24/16 , H01L29/0657 , H01L29/41766 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L2224/0401 , H01L2224/05599 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , Y10S438/977
摘要： A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate.
摘要翻译：提供了具有半导体衬底，外延层，至少MOS单元和金属图案层的金属氧化物半导体芯片。外延层位于半导体衬底上，并具有限定在其上表面上的有源区，端接区和划线保留区。外延层的蚀刻侧壁位于划线保留区域中。因此，半导体衬底的上表面的边界部分露出。 MOS单元位于活动区域。金属图案层位于外延层上，并且具有耦合到MOS单元的栅极的栅极焊盘，耦合到MOS单元的源极的源极焊盘和部分位于MOS单元的上表面上的漏极图案半导体衬底。

7. 发明申请

US20100330760A1 Fabrication method of trenched metal-oxide-semiconductor device 有权
标题翻译：沟槽金属氧化物半导体器件的制造方法
公开(公告)号：US20100330760A1
公开(公告)日：2010-12-30
申请号：US12457928
申请日：2009-06-25
申请人： Kao-Way Tu , Yen-Chih Huang
发明人： Kao-Way Tu , Yen-Chih Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/0878 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A fabrication method of trenched metal-oxide-semiconductor device is provided. A pattern layer with a plurality of openings is formed on a semiconductor base, and then a spacer is formed on the sidewall of the opening to define the gate trench. After the gate electrode formed in the gate trench, a dielectric structure is formed on the gate electrode by filling dielectric material into the opening. Then, the pattern layer and the spacer are removed and a dielectric layer is formed on the dielectric structure. The portion of the dielectric layer on the sidewall of the dielectric structure defines the source regions. After the source regions are formed in the well, another dielectric layer is formed on the dielectric layer to define the heavily doped regions adjacent to the source regions.
摘要翻译：提供了一种沟槽金属氧化物半导体器件的制造方法。在半导体基底上形成具有多个开口的图案层，然后在开口的侧壁上形成间隔物以限定栅极沟槽。在形成在栅极沟槽中的栅电极之后，通过将介电材料填充到开口中，在栅电极上形成电介质结构。然后，去除图案层和间隔物，并在电介质结构上形成电介质层。电介质结构侧壁上介电层的部分限定了源区。在阱中形成源极区之后，在电介质层上形成另一个介电层，以限定与源区相邻的重掺杂区。

8. 发明授权

US08399921B2 Metal oxide semiconductor (MOS) structure and manufacturing method thereof 有权
标题翻译：金属氧化物半导体（MOS）结构及其制造方法
公开(公告)号：US08399921B2
公开(公告)日：2013-03-19
申请号：US12567194
申请日：2009-09-25
申请人： Kao-Way Tu
发明人： Kao-Way Tu
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions.
摘要翻译：该制造方法包括以下步骤：提供第一导电类型的半导体基底; 在所述半导体基底的第一表面上形成具有多个外延柱的第一外延层，其中所述外延柱具有与所述第一外延层相反的导电类型; 在所述外延柱和所述第一外延层上交替地形成多个第一浅沟槽和多个第二浅沟槽，其中所述第一浅沟槽的宽度大于所述第二浅沟槽的宽度，并且所述第一浅沟槽向下延伸到外延柱; 以及分别在所述第一浅沟槽中形成多个栅极区域; 在所述第一浅沟槽的两侧形成多个源极区域; 以及形成源极金属导线以连接源极区域。

9. 发明授权

US08114762B2 Method for manufacturing trench MOSFET device with low gate charge 有权
标题翻译：具有低栅极电荷的沟槽MOSFET器件的制造方法
公开(公告)号：US08114762B2
公开(公告)日：2012-02-14
申请号：US12453281
申请日：2009-05-06
申请人： Hsiu-Wen Hsu , Chun Wei Ni , Kao-Way Tu
发明人： Hsiu-Wen Hsu , Chun Wei Ni , Kao-Way Tu
IPC分类号： H01L21/3205 , H01L21/44
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/407 , H01L29/42376 , H01L29/4933 , H01L29/66734
摘要： A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased.
摘要翻译：具有低栅极电荷的沟槽MOSFET器件的制造方法包括提供第一导电类型的衬底的步骤; 在衬底上形成第一导电类型的外延层; 在所述外延层中形成第二导电类型的体区，所述体区从所述外延层的表面向下延伸; 在所述外延层中形成多个沟槽，所述主体区域具有穿过其形成的沟槽; 在所述主体区域和每个沟槽的内表面上形成第一绝缘层; 在每个沟槽的内侧壁上的第一绝缘层上形成合金硅衬垫; 在每个沟槽的下部填充电介质结构; 并在每个沟槽中的电介质结构的顶部上填充硅 - 硅结构。通过沟槽MOSFET器件，栅极电容和电阻降低，从而性能提高。

10. 发明申请

US20100078737A1 High-voltage metal oxide semiconductor device and fabrication method thereof 有权
标题翻译：高压金属氧化物半导体器件及其制造方法
公开(公告)号：US20100078737A1
公开(公告)日：2010-04-01
申请号：US12285179
申请日：2008-09-30
申请人： Kao-Way Tu
发明人： Kao-Way Tu
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/407 , H01L29/42376 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L29/7813
摘要： A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.
摘要翻译：一种高电压金属氧化物半导体器件，包括第一导电类型的主体，导电结构，第二导电类型的第一阱，第一导电类型的源极区和第二导电类型的第二阱，提供。该导电结构具有第一部分和第二部分。第一部分从主体的上表面延伸到主体。第二部分沿着主体的上表面延伸。第一口井位于主体中，并位于第二部分之下。第一个井以预定距离远离第一部分。源区位于第一井。第二井位于主体中并且从第一部分的底部延伸到靠近排水区的位置。

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