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1. 发明授权

US09214343B2 ZNSNO3/ZNO nanowire having core-shell structure, method of forming ZNSNO3/ZNO nanowire and nanogenerator including ZNSNO3/ZNO nanowire, and method of forming ZNSNO3 nanowire and nanogenerator including ZNSNO3 nanowire 有权
标题翻译：具有核 - 壳结构的ZNSNO3 / ZNO纳米线，形成ZNSNO3 / ZNO纳米线的方法和ZNSNO3 / ZNO纳米线的纳米发生器，以及形成ZNSNO3纳米线和包含ZNSNO3纳米线的纳米发生器的方法
公开(公告)号：US09214343B2
公开(公告)日：2015-12-15
申请号：US13489200
申请日：2012-06-05
申请人： Jung-inn Sohn , Seung-Nam Cha , Sung-min Kim , Sang-woo Kim
发明人： Jung-inn Sohn , Seung-Nam Cha , Sung-min Kim , Sang-woo Kim
IPC分类号： H01L41/08 , H01L21/02 , H01L41/113 , H01L41/18 , H01L29/06
CPC分类号： H01L21/02645 , H01L21/0237 , H01L21/02472 , H01L21/02483 , H01L21/02513 , H01L21/02554 , H01L21/02603 , H01L21/02631 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L41/113 , H01L41/18
摘要： A ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3/ZnO nanowire, a nanogenerator including a ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3 nanowire, and a nanogenerator including a ZnSnO3 nanowire are provided. The ZnSnO3/ZnO nanowire includes a core and a shell that surrounds the core, wherein the core includes ZnSnO3 and the shell includes ZnO.
摘要翻译：提供ZnSnO 3 / ZnO纳米线，形成ZnSnO 3 / ZnO纳米线的方法，包括ZnSnO 3 / ZnO纳米线的纳米发生器，形成ZnSnO 3纳米线的方法和包含ZnSnO 3纳米线的纳米发生器。 ZnSnO 3 / ZnO纳米线包括芯和围绕芯的壳，其中芯包括ZnSnO 3，壳包括ZnO。

2. 发明授权

US09270207B2 Nano generator and method of manufacturing the same 有权
标题翻译：纳米发生器及其制造方法
公开(公告)号：US09270207B2
公开(公告)日：2016-02-23
申请号：US13412285
申请日：2012-03-05
申请人： Jung-inn Sohn , Seung-nam Cha , Sung-min Kim , Sang-woo Kim , Ju-seok Seo
发明人： Jung-inn Sohn , Seung-nam Cha , Sung-min Kim , Sang-woo Kim , Ju-seok Seo
IPC分类号： H01L41/113 , H02N2/18 , H01L41/45 , H01L41/193
CPC分类号： H01L41/45 , H01L41/1136 , H01L41/193 , H02N2/18 , H02N11/002 , Y10T29/42
摘要： A nanogenerator with at least one nanostructure and method of manufacturing the same are provided. The method of manufacturing the nanogenerator includes forming at least one nanostructure including an organic piezoelectric material on a substrate.
摘要翻译：提供具有至少一种纳米结构的纳米发生器及其制造方法。制造纳米发生器的方法包括在衬底上形成包括有机压电材料的至少一个纳米结构。

3. 发明授权

US09190605B2 Nanopiezoelectric generator and method of manufacturing the same 有权
标题翻译：纳米压电发电机及其制造方法
公开(公告)号：US09190605B2
公开(公告)日：2015-11-17
申请号：US13561509
申请日：2012-07-30
申请人： Seung-nam Cha , Sung-min Kim , Jung-inn Sohn
发明人： Seung-nam Cha , Sung-min Kim , Jung-inn Sohn
IPC分类号： H01L41/113 , H01L41/29 , H01L41/18 , H01L41/253
CPC分类号： H01L41/29 , H01L41/113 , H01L41/18 , H01L41/253
摘要： A nanopiezoelectric generator is provided. The nanopiezoelectric generator includes a first electrode; a second electrode; at least one nanostructure that is interposed between the first electrode and the second electrode, and includes a piezoelectric material and first carriers; and a concentration adjusting unit that adjusts a concentration of the first carriers in the at least one nanostructure.
摘要翻译：提供了一种纳米氧电发生器。所述纳米氧电发生器包括第一电极; 第二电极; 介于所述第一电极和所述第二电极之间的至少一个纳米结构，并且包括压电材料和第一载体; 以及浓度调节单元，其调节至少一个纳米结构中的第一载流子的浓度。

4. 发明授权

US08975805B2 Electrical energy generator 有权
标题翻译：电能发电机
公开(公告)号：US08975805B2
公开(公告)日：2015-03-10
申请号：US13396208
申请日：2012-02-14
申请人： Sung-min Kim , Seung-nam Cha
发明人： Sung-min Kim , Seung-nam Cha
IPC分类号： H01L41/113
CPC分类号： H02N2/186 , Y02E10/549
摘要： According to an example embodiment, an electrical energy generator includes at least one piezoelectric structure, a semiconductor layer and a contact layer. The at least one piezoelectric structure includes a material having piezoelectric characteristics. One surface of each piezoelectric structure forms a p-n junction with the semiconductor layer. The other end of each piezoelectric structure contacts the contact layer that is formed of a material having metal-insulator transition (MIT) characteristics. The piezoelectric structure may be an elongated member, such as a nanowire.
摘要翻译：根据示例性实施例，电能发生器包括至少一个压电结构，半导体层和接触层。所述至少一个压电结构包括具有压电特性的材料。每个压电结构的一个表面与半导体层形成p-n结。每个压电结构的另一端接触由具有金属 - 绝缘体转变（MIT）特性的材料形成的接触层。压电结构可以是细长构件，例如纳米线。

5. 发明授权

US08908052B2 Method and apparatus for correcting shakiness 有权
标题翻译：纠正抖动的方法和装置
公开(公告)号：US08908052B2
公开(公告)日：2014-12-09
申请号：US12949169
申请日：2010-11-18
申请人： Sung-min Kim , Jin-gi Lee
发明人： Sung-min Kim , Jin-gi Lee
IPC分类号： H04N5/232
CPC分类号： H04N5/23248 , H04N5/23258 , H04N5/23261
摘要： Provided is a method, apparatus, and computer readable medium for correcting shakiness, in which the method includes generating using a hall sensor a hall sensor signal corresponding to displacement caused by a shock; determining whether the hall sensor signal exceeds a first threshold value; generating a shakiness correction control signal according to a result of the determination; and performing shakiness correction according to the shakiness correction control signal.
摘要翻译：提供了一种用于校正抖动的方法，装置和计算机可读介质，其中该方法包括使用霍尔传感器产生对应于由冲击引起的位移的霍尔传感器信号; 确定所述霍尔传感器信号是否超过第一阈值; 根据确定的结果产生抖动校正控制信号; 并根据抖动校正控制信号进行抖动校正。

6. 发明授权

US08046054B2 Bi-planar fluoroscopy guided robot system for minimally invasive surgery and the control method thereof 有权
标题翻译：用于微创手术的双平面荧光透视引导机器人系统及其控制方法
公开(公告)号：US08046054B2
公开(公告)日：2011-10-25
申请号：US11530653
申请日：2006-09-11
申请人： Young Soo Kim , Byung-Ju Yi , Jong-Il Park , Sung-min Kim , Se-Min Oh
发明人： Young Soo Kim , Byung-Ju Yi , Jong-Il Park , Sung-min Kim , Se-Min Oh
IPC分类号： A61B5/05
CPC分类号： A61B6/4014 , A61B6/4441 , A61B34/10 , A61B34/30 , A61B2090/376
摘要： Disclosed is a computer-integrated surgery aid system for minimally invasive surgery and a method for controlling the same. The system includes a surgery planning system for creating three-dimensional information from two-dimensional images obtained by means of biplanar fluoroscopy so that spinal surgery can be planned according to the image information and a scalar-type 6 degree-of-freedom surgery aid robot adapted to be either driven automatically or operated manually.
摘要翻译：公开了一种用于微创手术的计算机一体化手术辅助系统及其控制方法。该系统包括用于通过双平面荧光透视获得的二维图像创建三维信息的手术计划系统，使得可以根据图像信息和标量型6自由度手术辅助机器人计划脊柱手术适于自动驱动或手动操作。

7. 发明授权

US08008141B2 Method of fabricating a semiconductor device with multiple channels 有权
标题翻译：制造具有多个通道的半导体器件的方法
公开(公告)号：US08008141B2
公开(公告)日：2011-08-30
申请号：US12503594
申请日：2009-07-15
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L21/8232
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

8. 发明申请

US20090239346A1 SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有FINFET的半导体器件及其制造方法
公开(公告)号：US20090239346A1
公开(公告)日：2009-09-24
申请号：US12477348
申请日：2009-06-03
申请人： Sung-min Kim , Min-sang Kim , Eun-jung Yun
发明人： Sung-min Kim , Min-sang Kim , Eun-jung Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.
摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。第一突起和第二突起的上表面和侧表面包括通道区域。通道离子注入层设置在中央沟槽的底部和鳍片的下部。在鳍片上设置栅极氧化层。栅电极设置在栅氧化层上。源极区域和漏极区域设置在栅电极侧的有源区域中。还提供了一种形成这种装置的方法。

9. 发明申请

US20090168493A1 SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储器单元的方法
公开(公告)号：US20090168493A1
公开(公告)日：2009-07-02
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00 , H01L21/00 , H01L47/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

10. 发明授权

US07442987B2 Non-volatile memory devices including divided charge storage structures 失效
标题翻译：非易失性存储器件包括分开的电荷存储结构
公开(公告)号：US07442987B2
公开(公告)日：2008-10-28
申请号：US12014276
申请日：2008-01-15
申请人： Sung-min Kim , Dong-won Kim , Eun-jung Yun
发明人： Sung-min Kim , Dong-won Kim , Eun-jung Yun
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.
摘要翻译：半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层，第一和第二电荷存储层。栅电极远离基板延伸超过第一和第二电荷存储层。该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。还讨论了相关的制造方法。

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