专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110078692A1 COALESCING MEMORY BARRIER OPERATIONS ACROSS MULTIPLE PARALLEL THREADS 有权
标题翻译：通过多个并行线程来解决存储器障碍操作
公开(公告)号：US20110078692A1
公开(公告)日：2011-03-31
申请号：US12887081
申请日：2010-09-21
申请人： John R. NICKOLLS , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
发明人： John R. NICKOLLS , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
IPC分类号： G06F9/46
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for coalescing memory barrier operations across multiple parallel threads. Memory barrier requests from a given parallel thread processing unit are coalesced to reduce the impact to the rest of the system. Additionally, memory barrier requests may specify a level of a set of threads with respect to which the memory transactions are committed. For example, a first type of memory barrier instruction may commit the memory transactions to a level of a set of cooperating threads that share an L1 (level one) cache. A second type of memory barrier instruction may commit the memory transactions to a level of a set of threads sharing a global memory. Finally, a third type of memory barrier instruction may commit the memory transactions to a system level of all threads sharing all system memories. The latency required to execute the memory barrier instruction varies based on the type of memory barrier instruction.
摘要翻译：本发明的一个实施例提出了一种用于在多个并行线程之间聚合存储器屏障操作的技术。来自给定并行线程处理单元的存储器屏障请求被合并以减少对系统其余部分的影响。此外，存储器屏障请求可以指定针对其提交内存事务的一组线程的级别。例如，第一类型的存储器障碍指令可以将存储器事务提交到共享L1（一级）高速缓存的一组协作线程的级别。第二种类型的存储器障碍指令可以将存储器事务提交到共享全局存储器的一组线程的级别。最后，第三种类型的存储器障碍指令可以将存储器事务提交到共享所有系统存储器的所有线程的系统级。执行存储器屏障指令所需的延迟基于存储器屏障指令的类型而变化。

2. 发明申请

US20110072213A1 INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY 有权
标题翻译：用于管理并行缓存高速缓存的指令
公开(公告)号：US20110072213A1
公开(公告)日：2011-03-24
申请号：US12888409
申请日：2010-09-22
申请人： John R. NICKOLLS , Brett W. Coon , Michael C. Shebanow
发明人： John R. NICKOLLS , Brett W. Coon , Michael C. Shebanow
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F9/3887 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/121 , G06F2212/452
摘要： A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.
摘要翻译：一种用于在处理单元中管理并行高速缓存层级的方法。该方法包括从调度器单元接收指令，其中指令包括加载指令或存储指令; 确定所述指令包括高速缓存操作修饰符，所述缓存操作修饰符标识用于缓存与所述并行高速缓存层级的一个或多个级别上的所述指令相关联的数据的并且基于高速缓存操作修饰符执行指令并缓存与指令相关联的数据。

3. 发明申请

US20110072248A1 UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR 有权
标题翻译：并行螺纹加工器中的分支分支指令
公开(公告)号：US20110072248A1
公开(公告)日：2011-03-24
申请号：US12815201
申请日：2010-06-14
申请人： John R. NICKOLLS , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
发明人： John R. NICKOLLS , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.
摘要翻译：本发明的一个实施例提出了一种用于管理执行多线程处理器的线程组中的线程发散的机制。一致的分支指令执行时，只有当线程组中的每个线程同意采用分支时，才能使线程组中的所有活动线程分支。以这种方式消除螺纹发散。分支 - 任何指令执行时，会导致线程组中的所有活动线程在线程组中的至少一个线程同意分支时分支。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式