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1. 发明授权

US08029975B2 Fused aromatic structures and methods for photolithographic applications 有权
标题翻译：熔融芳族结构和光刻应用的方法
公开(公告)号：US08029975B2
公开(公告)日：2011-10-04
申请号：US12508652
申请日：2009-07-24
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/004 , G03F7/039 , G03F7/20 , G03F7/30 , G03F7/38
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

2. 发明申请

US20090004596A1 FUSED AROMATIC STRUCTURES AND METHODS FOR PHOTOLITHOGRAPHIC APPLICATIONS 失效
公开(公告)号：US20090004596A1
公开(公告)日：2009-01-01
申请号：US11769089
申请日：2007-06-27
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03C1/73 , G03C5/00
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.

3. 发明申请

US20090286180A1 FUSED AROMATIC STRUCTURES AND METHODS FOR PHOTOLITHOGRAPHIC APPLICATIONS 有权
标题翻译：用于光刻应用的熔融芳构结构和方法
公开(公告)号：US20090286180A1
公开(公告)日：2009-11-19
申请号：US12508652
申请日：2009-07-24
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/20 , G03F7/004
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

4. 发明授权

US07566527B2 Fused aromatic structures and methods for photolithographic applications 失效
标题翻译：熔融芳族结构和光刻应用的方法
公开(公告)号：US07566527B2
公开(公告)日：2009-07-28
申请号：US11769089
申请日：2007-06-27
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/039 , G03F7/20 , G03F7/30 , G03F7/36 , G03F7/38
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

5. 发明申请

US20100196806A1 STRUCTURES AND METHODS FOR LOW-K OR ULTRA LOW-K INTERLAYER DIELECTRIC PATTERN TRANSFER 审中-公开
标题翻译：低K或超低介电常数介质转移的结构与方法
公开(公告)号：US20100196806A1
公开(公告)日：2010-08-05
申请号：US12758431
申请日：2010-04-12
申请人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
发明人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
IPC分类号： G03F1/00
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
摘要翻译：本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层，用于随后的图案转印的上氧化物掩模层。接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。

6. 发明授权

US07695897B2 Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer 失效
标题翻译：低k或超低k层间电介质图案转移的结构和方法
公开(公告)号：US07695897B2
公开(公告)日：2010-04-13
申请号：US11429709
申请日：2006-05-08
申请人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
发明人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
IPC分类号： G03F7/00 , G03F7/26
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
摘要翻译：本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层，用于随后的图案转印的上氧化物掩模层。接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。

7. 发明授权

US09259902B2 4D Device, process and structure 有权
标题翻译： 4D设备，过程和结构
公开(公告)号：US09259902B2
公开(公告)日：2016-02-16
申请号：US13353183
申请日：2012-01-18
申请人： Roy R. Yu , Wilfried Haensch
发明人： Roy R. Yu , Wilfried Haensch
IPC分类号： H01L21/98 , B32B37/02 , H01L23/473 , H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00 , B32B37/12 , B32B38/18 , H01L29/06
CPC分类号： B32B37/02 , B32B37/12 , B32B38/1841 , B32B2309/105 , B32B2310/0843 , B32B2457/14 , H01L23/473 , H01L23/481 , H01L23/49827 , H01L24/09 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/0401 , H01L2224/05144 , H01L2224/05147 , H01L2224/06181 , H01L2224/08145 , H01L2224/13147 , H01L2224/16147 , H01L2224/26135 , H01L2224/291 , H01L2224/29147 , H01L2224/2919 , H01L2224/32145 , H01L2224/73253 , H01L2224/81191 , H01L2224/83005 , H01L2224/8314 , H01L2224/83141 , H01L2224/9202 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1032 , H01L2924/10329 , H01L2924/1204 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/15153 , H01L2224/83 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00
摘要： A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling, and is further diced at the fixed clock-cycle distance, and flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.
摘要翻译： 4D设备包括2D多核逻辑和通过存储器堆叠侧壁使用细间距T＆J连接连接的3D存储器堆栈。堆叠中的3D存储器从原始晶片厚度减薄到没有剩余的Si。存储晶片顶部和底部表面上的舌形槽装置允许精确的堆叠对准。存储器堆栈还在背面具有微通道以允许流体冷却，并且以固定的时钟周期距离进一步切割，并在其侧面翻转并且重新组装到模板上成为伪晶片格式。组件的顶侧壁被抛光并用BEOL构建以扇出，并且使用T＆J细间距连接来连接到2D逻辑晶片。存储器堆叠的另一面被抛光，扇形，并用C4焊料撞击。本发明还包括一种制造该装置的方法。

8. 发明授权

US08563396B2 3D integration method using SOI substrates and structures produced thereby 有权
标题翻译：使用SOI衬底的3D集成方法和由此产生的结构
公开(公告)号：US08563396B2
公开(公告)日：2013-10-22
申请号：US13016994
申请日：2011-01-29
申请人： Sampath Purushothaman , Roy R. Yu
发明人： Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L21/60
CPC分类号： H01L21/76897 , H01L21/304 , H01L21/30604 , H01L21/76251 , H01L21/76256 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76879 , H01L21/76898 , H01L21/84 , H01L23/5226 , H01L23/544 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/89 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L27/1207 , H01L29/0649 , H01L2221/68372 , H01L2223/54426 , H01L2224/03002 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/11002 , H01L2224/1148 , H01L2224/11616 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/17181 , H01L2224/8013 , H01L2224/81005 , H01L2224/81065 , H01L2224/81075 , H01L2224/8109 , H01L2224/81093 , H01L2224/81193 , H01L2224/81201 , H01L2224/81209 , H01L2224/9202 , H01L2224/94 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
摘要翻译：通过这种方法制造的工艺和最终的制品包括将包含硅绝缘体（SOI）的顶部硅晶片中的将底部硅晶片中的底部器件层连接到顶部器件层中的底部器件层所需的通孔形成，晶圆。通孔以这样的方式设置，使得它们从顶部晶片的线（MOL）互连的中间延伸到SOI晶片的掩埋氧化物（BOX）层，其中提供了适当的绝缘以将它们与SOI器件层隔离开。

9. 发明授权

US08298914B2 3D integrated circuit device fabrication using interface wafer as permanent carrier 有权
标题翻译：使用接口晶片作为永久载体的3D集成电路器件制造
公开(公告)号：US08298914B2
公开(公告)日：2012-10-30
申请号：US12194198
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/4763
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。还提供了一种用包括用于执行这种方法的指令的程序编码的有形计算机可读介质。

10. 发明授权

US08129256B2 3D integrated circuit device fabrication with precisely controllable substrate removal 有权
标题翻译： 3D集成电路器件制造具有精确可控的衬底去除
公开(公告)号：US08129256B2
公开(公告)日：2012-03-06
申请号：US12194065
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

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