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1. 发明授权

US08150326B2 Signal processing for multi-sectored wireless communications system and method thereof 有权
标题翻译：多扇区无线通信系统的信号处理及其方法
公开(公告)号：US08150326B2
公开(公告)日：2012-04-03
申请号：US12516587
申请日：2007-12-28
申请人： James Awuor Oduor Okello , Katsutoshi Seki
发明人： James Awuor Oduor Okello , Katsutoshi Seki
IPC分类号： H04B1/00 , H04B15/00
CPC分类号： H04B7/0491
摘要： Disclosed is a signal processing system in a base station that receives and processes single carrier or multiple carrier signals from transmitting units in a sectored coverage area with at least one transmit antenna and at least one receive antenna, the signal power gain between transmit and receive antennas within each sector being represented as a channel matrix with path gains. The system comprises: a detection unit that determines if signals from a given target transmitting unit is available in the signal received in a sector, and generates a detect signal for a combination unit; a decision unit that selects size of interference cancellation matrix; and an interference cancellation unit. When the signal from detection unit indicates that signal from a target transmitting unit is in the signal associated with at least two sectors, the decision unit joins channel matrices associated with the sectors to generate a large channel matrix, and using the resulting large channel matrix, the interference cancellation unit eliminates interference or generates originally transmitted signal. When the signal from detection unit indicates that signal from a target transmitting unit is in the signal of only one sector, the interference cancellation unit eliminates interference from the received signal, using the channel matrix associated with the one sector.
摘要翻译：公开了一种基站中的信号处理系统，其接收并处理具有至少一个发射天线和至少一个接收天线的扇区覆盖区域中的发射单元的单载波或多载波信号，即发射天线和接收天线之间的信号功率增益在每个扇区内被表示为具有路径增益的信道矩阵。该系统包括：检测单元，其确定来自给定目标发送单元的信号在扇区中接收的信号中是否可用，并且生成用于组合单元的检测信号; 选择干扰消除矩阵的大小的判定单元; 和干扰消除单元。当来自检测单元的信号指示来自目标发送单元的信号处于与至少两个扇区相关联的信号中时，判决单元加入与扇区相关联的信道矩阵以生成大信道矩阵，并且使用所得到的大信道矩阵，干扰消除单元消除干扰或产生原始发送的信号。当来自检测单元的信号指示来自目标发送单元的信号仅在一个扇区的信号中时，干扰消除单元使用与该扇区相关联的信道矩阵来消除来自接收信号的干扰。

2. 发明申请

US20110059713A1 SIGNAL PROCESSING FOR MULTI-SECTORED WIRELESS COMMUNICATIONS SYSTEM AND METHOD THEREOF 有权
标题翻译：多级无线通信系统的信号处理及其方法
公开(公告)号：US20110059713A1
公开(公告)日：2011-03-10
申请号：US12516587
申请日：2007-12-28
申请人： James Awuor Oduor Okello , Katsutoshi Seki
发明人： James Awuor Oduor Okello , Katsutoshi Seki
IPC分类号： H04B1/10
CPC分类号： H04B7/0491
摘要： The present invention provides an apparatus and a method that realize dynamically processing signals received from multiple sectors to increase throughput of uplink communications in a multi-sectored wireless base station. The signal streams received from sector-1 (25) and (26) and signal streams received from sector-2 (27) and (28) are concentrated in a unit (105). Similarly, channel parameters (29) and (30) from sector-1 and sector-2, respectively, are used to create a modified channel matrix, dimension of which is much larger than that of each of channel matrices of respective sectors. Dynamic processing of signals received from multiple sectors is done by a detection unit (103) which receive channel parameters (131) or (133), and, a comparison unit (104). Signals from a transmitting unit are detected within the signals received from two or more sectors, or the same signals are detected within the signal received from one sector. Based on the results of the comparison unit (104), a modified channel matrix and received signal vector from one sector is selected in a channel matrix selection unit (102) and used in a unit (21) to perform interference cancellation.
摘要翻译：本发明提供一种实现动态处理从多个扇区接收的信号以增加多扇区无线基站中的上行链路通信的吞吐量的装置和方法。从扇区-1（25）和（26）接收的信号流和从扇区2（27）和（28）接收的信号流集中在一个单元（105）中。类似地，来自扇区1和扇区-2的信道参数（29）和（30）分别用于创建修改的信道矩阵，其维数远大于相应扇区的每个信道矩阵的维数。通过接收信道参数（131）或（133）的检测单元（103）和比较单元（104）来完成从多个扇区接收的信号的动态处理。在从两个或多个扇区接收的信号内检测来自发送单元的信号，或者在从一个扇区接收的信号内检测到相同的信号。基于比较单元（104）的结果，在信道矩阵选择单元（102）中选择修改的信道矩阵和来自一个扇区的接收信号向量，并在单元（21）中使用以执行干扰消除。

3. 发明授权

US09286066B2 Processor, and method of loop count control by processor 有权
标题翻译：处理器和处理器的循环计数控制方法
公开(公告)号：US09286066B2
公开(公告)日：2016-03-15
申请号：US13508977
申请日：2010-10-15
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34
CPC分类号： G06F9/30065 , G06F9/30101 , G06F9/325 , G06F9/34
摘要： A processor includes a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued, a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside, a calculator that uses the data transferred to the data memory to execute the process in the loop, a data counter that increments the loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, and a loop controller that decrements the loop counter by 1 and causes the calculator to execute the process in the loop when a loop count value of the loop counter is not 0.
摘要翻译：处理器包括循环计数器，当从循环起始地址到循环结束地址的循环执行循环指令时，循环计数器被重置为0;数据存储器，其接收用于执行循环起始地址中的处理的数据循环，其中数据从外部传送，计算器，其使用传送到数据存储器的数据来执行循环中的处理;数据计数器，每当使用一定量的数据时，将循环计数器递增1 用于执行循环中的处理从外部传送到数据存储器，以及循环控制器，其将循环计数器递减1，并且使得当循环计数器的循环计数值不为0时，计算器执行循环中的处理。

4. 发明申请

US20100250640A1 SYSTOLIC ARRAY AND CALCULATION METHOD 有权
标题翻译： SYSTOLIC ARRAY和计算方法
公开(公告)号：US20100250640A1
公开(公告)日：2010-09-30
申请号：US12744450
申请日：2008-11-21
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F17/16 , G06F9/302
CPC分类号： G06F17/16 , G06F15/8046
摘要： A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay.
摘要翻译：通过组合三角收缩阵列和方波收缩阵列产生的梯形心脏收缩阵列的下侧添加线性收缩阵列。为了使固定的单元之间的连接，将梯形收缩阵列的每一行输出到下一行的中间结果相对于复合MFA算法的中间结果相位移位，相移被并且通过线性收缩阵列校正来自梯形脉波收缩阵列的最后一行的中间结果输出中的相移。每个单元由CORDIC电路实现，该电路处理矢量角计算，向量旋转，除法，并以恒定延迟进行乘法和累加。

5. 发明申请

US20070033482A1 Decoder device and decoding method and program 失效
标题翻译：解码器及解码方法及程序
公开(公告)号：US20070033482A1
公开(公告)日：2007-02-08
申请号：US11476686
申请日：2006-06-29
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： H03M13/00
CPC分类号： H03M13/11
摘要： A device and a method that improve decoding characteristics of an LDPC decoder to which SPA where the equation for the computation of messages is approximated and the number of messages are reduced is applied. A received LDPC code is decoded by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix, and messages sent from one of the check nodes to one of the bit nodes out of messages sent from the one of bit nodes to the one of check nodes are weighted at the one of bit nodes so that the longer ago the messages are computed at the one of check nodes, the less influential they become.
摘要翻译：应用一种改进解码特征的装置和方法，该LDPC解码器的解码特性使消息的计算方程近似的SPA被缩小，消息的数量减少到该解码器的解码特性。通过重复在多个校验节点与对应于校验矩阵的多个比特节点之间的消息的传递以及从校验节点之一发送到其中一个比特节点的消息之外的消息来解码接收到的LDPC码。一个校验节点的位节点中的一个被加权在位节点之一处，使得较长时间的消息在校验节点之一处被计算，影响较小。

6. 发明授权

US06259729B1 Method of and an apparatus for training tap coefficients of an adaptive equalizer 失效
标题翻译：用于训练自适应均衡器的抽头系数的方法和装置
公开(公告)号：US06259729B1
公开(公告)日：2001-07-10
申请号：US09216024
申请日：1998-12-18
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： H03H730
CPC分类号： H04L25/03133 , H04L2025/03414 , H04L2025/0377
摘要： For training tap coefficients of an adaptive equalizer of L taps to be used for equalizing an impulse response of a transmission channel (200) to be shorter than v taps, stably and speedily, a training circuit comprises: a transmitter (100) for transmitting a transmission signal (x(D)) produced by converting a frequency-domain transmission vector (X) encoded with a PRBS into a time-domain; a target-impulse-response update means (1300) for producing an updated target impulse response (Bu) making use of frequency-domain division method referring to windowed tap coefficients (ww(D)), a reception signal (y(D)), and a training vector (X) encoded with a replica of the PRBS; a target-impulse-response windowing means (1400) for outputting a windowed target impulse response (Bw) together wit a normalization coefficient (S) by windowing and normalizing the updated target impulse response (Bu) within L taps in a time-domain; a tap-coefficient update means (2500) for updating the windowed tap coefficients (ww(D)) making use of a frequency-domain LMS method referring to the normalization coefficient (S), the windowed target impulse response (Bw), the training vector (X′) and the reception signal (y(D)); and a tap-coefficient windowing means (1600) for windowing the updated tap coefficients into v taps. By updating the windowed tap coefficients (ww(D)) repeatedly until a certain convergence condition is attained, the windowed tap coefficients (ww(D)) are outputted as the tap coefficients of the adaptive equalizer.
摘要翻译：为了训练用于将传输信道（200）的脉冲响应均衡到比v抽头更短的L抽头的自适应均衡器的抽头系数稳定且快速地，培训电路包括：发送器（100），用于发送通过将由PRBS编码的频域传输矢量（X）转换成时域而产生的传输信号（x（D））; 一个目标脉冲响应更新装置，用于产生使用参考窗口抽头系数（ww（D））的频域分割方法的更新的目标脉冲响应（Bu），接收信号（y（D））以及用PRBS的副本编码的训练向量（X）; 目标脉冲响应窗口装置（1400），用于通过在时域中的L个抽头内对所更新的目标脉冲响应（Bu）进行加窗和归一化来将加窗目标脉冲响应（Bw）与归一化系数（S）一起输出; 抽头系数更新装置（2500），用于使用参考标准化系数（S）的频域LMS方法来更新加窗抽头系数（ww（D）），窗口化目标脉冲响应（Bw），训练矢量（X'）和接收信号（y（D））; 以及用于将更新的抽头系数加窗成v抽头的抽头系数窗口装置（1600）。通过重复更新加窗抽头系数（ww（D））直到获得一定的收敛条件，则窗口抽头系数（ww（D））被输出为自适应均衡器的抽头系数。

7. 发明授权

US09002919B2 Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method 有权
标题翻译：数据重排电路，可变延迟电路，快速傅立叶变换电路和数据重排方法
公开(公告)号：US09002919B2
公开(公告)日：2015-04-07
申请号：US13497553
申请日：2010-06-03
申请人： Yuki Kobayashi , Katsutoshi Seki
发明人： Yuki Kobayashi , Katsutoshi Seki
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F5/08 , G06F5/10 , G06F7/762 , G06F7/78 , G06F2205/104
摘要： A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.
摘要翻译：数据重排电路包括可变延迟装置和控制装置。可变延迟通过给每个输入周期不同的延迟周期的延迟，以及对于每个端口对作为多个端口和多个端口的输入的数据组的每个数据单元的延迟循环，切换同一端口中数据的顺序，并以预定的延迟提供数据作为数据组。控制装置提供包括在可变延迟装置中使用的延迟周期数的控制信息。

8. 发明授权

US08572152B2 CORDIC computation circuit and method 有权
标题翻译： CORDIC计算电路及方法
公开(公告)号：US08572152B2
公开(公告)日：2013-10-29
申请号：US12919632
申请日：2009-03-05
申请人： Katsutoshi Seki
发明人： Katsutoshi Seki
IPC分类号： G06F7/38
CPC分类号： G06F7/5446 , G06T3/604
摘要： Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.
摘要翻译：公开了一种CORDIC电路，其中缩放校正处理被分为两个阶段：粗略校正和精细校正，并且与精细刻度校正并行执行伪旋转处理的第二处理。精确刻度校正的范围被设定为不需要对伪旋转处理的前半部分的剩余旋转角进行刻度校正。

9. 发明申请

US20120278373A1 DATA REARRANGING CIRCUIT, VARIABLE DELAY CIRCUIT, FAST FOURIER TRANSFORM CIRCUIT, AND DATA REARRANGING METHOD 有权
标题翻译：数据后置电路，可变延迟电路，快速傅立叶变换电路和数据重新排列方法
公开(公告)号：US20120278373A1
公开(公告)日：2012-11-01
申请号：US13497553
申请日：2010-06-03
申请人： Yuki Kobayashi , Katsutoshi Seki
发明人： Yuki Kobayashi , Katsutoshi Seki
IPC分类号： H03H11/26 , G06F17/14
CPC分类号： G06F17/142 , G06F5/08 , G06F5/10 , G06F7/762 , G06F7/78 , G06F2205/104
摘要： A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.
摘要翻译：数据重排电路包括可变延迟装置和控制装置。可变延迟通过给每个输入周期不同的延迟周期的延迟，以及对于每个端口对作为多个端口和多个端口的输入的数据组的每个数据单元的延迟循环，切换同一端口中数据的顺序，并以预定的延迟提供数据作为数据组。控制装置提供包括在可变延迟装置中使用的延迟周期数的控制信息。

10. 发明申请

US20100131738A1 ARRAY PROCESSOR TYPE DATA PROCESSING APPARATUS 有权
标题翻译：阵列处理器类型数据处理设备
公开(公告)号：US20100131738A1
公开(公告)日：2010-05-27
申请号：US12594757
申请日：2008-02-22
申请人： Tomoyoshi Kobori , Katsutoshi Seki
发明人： Tomoyoshi Kobori , Katsutoshi Seki
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/8046 , G06F15/17381 , G06T1/20
摘要： In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
摘要翻译：在阵列处理部分中，使用从输入端口输入的数据串，多个数据处理器元件在彼此传送数据的同时执行预定的操作，并从多个输出端口输出操作结果的数据串。第一数据串转换器将存储在数据存储组的多个数据存储器中的数据串转换成适用于阵列处理部分中的操作的放置，并将转换的数据串输入到阵列处理部分的输入端口。第二数据串转换器将从阵列处理部分的输出端口输出的数据串转换为要存储在数据存储组的多个数据存储器中的放置。

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