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1. 发明申请

WO2007016047A2 METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES 审中-公开
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：WO2007016047A2
公开(公告)日：2007-02-08
申请号：PCT/US2006/028718
申请日：2006-07-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GAIDIS, Michael, C. , RADENS, Carl , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HSU, Louis, L.c. , WONG, Keith Kwong Hon , YANG, Chih-chao
发明人： GAIDIS, Michael, C. , RADENS, Carl , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HSU, Louis, L.c. , WONG, Keith Kwong Hon , YANG, Chih-chao
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

2. 发明申请

WO2009142655A1 STRUCTURE AND PROCESS FOR CONDUCTIVE CONTACT INTEGRATION 审中-公开
标题翻译：导电接触集成的结构与工艺
公开(公告)号：WO2009142655A1
公开(公告)日：2009-11-26
申请号：PCT/US2008/077375
申请日：2008-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , GIGNAC, Lynne M.
发明人： YANG, Chih-chao , GIGNAC, Lynne M.
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.
摘要翻译：提供了一种半导体结构，其包括消除了键孔形成的高可靠性高纵横比接触结构。在本发明中通过在存在于电介质材料中的高纵横比接触开口内提供致密的含贵金属衬里来消除键孔缝形成。致密化的含贵金属的衬里位于扩散阻挡层的顶部，并且这两个元件将本发明接触结构的导电材料与下面的半导体结构的导电材料分开。通过沉积具有第一电阻率的含贵金属的材料形成本发明的含致密化的含贵金属的衬里，并使沉积的含贵金属的材料经受降低电阻率的致密化处理（热或等离子体）的沉积的含贵金属材料的电阻率较低。

3. 发明申请

WO2008036115A1 NOVEL STRUCTURE AND METHOD FOR METAL INTEGRATION 审中-公开
标题翻译：金属整合的新结构和方法
公开(公告)号：WO2008036115A1
公开(公告)日：2008-03-27
申请号：PCT/US2007/005414
申请日：2007-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , SPOONER, Terry, A. , VAN DER STRATEN, Oscar
发明人： YANG, Chih-chao , SPOONER, Terry, A. , VAN DER STRATEN, Oscar
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31105 , H01L21/31144 , H01L21/32131 , H01L21/76805 , H01L21/76808 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.
摘要翻译：提供了包括在一个通孔开口的底部的气泡特征的互连结构及其形成方法。根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的介电材料的损伤。根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。根据本发明，通过在形成线路开口和扩散阻挡层在所述线路开口中的沉积之前，在通孔开口的底部提供气泡特征来实现这种互连结构。

4. 发明申请

WO2014120337A1 ELECTRONIC FUSE HAVING AN INSULATION LAYER 审中-公开
标题翻译：具有绝缘层的电子保险丝
公开(公告)号：WO2014120337A1
公开(公告)日：2014-08-07
申请号：PCT/US2013/073776
申请日：2013-12-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BURKE, Chad, M. , LI, Baozhen , WONG, Keith Kwong, Hon , YANG, Chih-chao
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/28
CPC分类号： H01L23/5256 , H01L21/76877 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electronic fuse structure (200) including etching a dual damascene feature in a dielectric layer (214), the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line (220), a first via (222), and a second via (224). The structure further including forming an insulating layer (226) on top of the fuse line, and forming a fill material (228) on top of the insulating layer and substantially filling the trench opening.
摘要翻译：一种电子熔丝结构（200），包括在电介质层（214）中蚀刻双镶嵌特征，所述双镶嵌特征包括第一通孔开口，第二通孔开口和沟槽开口，在双镶嵌特征内形成种子层所述种子层包括导电材料，并且加热所述电介质层和所述晶种层，使所述种子层回流并填充所述第一通孔开口，所述第二通孔开口，并部分地填充所述沟槽开口以形成熔丝线（220），第一通孔（222）和第二通孔（224）。所述结构还包括在所述熔丝线的顶部上形成绝缘层（226），并且在所述绝缘层的顶部上形成填充材料（228）并且基本上填充所述沟槽开口。

5. 发明申请

WO2008045989A2 ENHANCED INTERCONNECT STRUCTURE 审中-公开
标题翻译：增强的互连结构
公开(公告)号：WO2008045989A2
公开(公告)日：2008-04-17
申请号：PCT/US2007/081046
申请日：2007-10-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , YANG, Haining, S. , WONG, Keith, Kwong Hon , FAROOQ, Mukta, G.
发明人： YANG, Chih-chao , YANG, Haining, S. , WONG, Keith, Kwong Hon , FAROOQ, Mukta, G.
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the interface of the capping layer (61), the underlying dielectric layer (12) and the diffusion barrier (31). The interconnect structure has a portion (41) of the diffusion barrier material (31) embedded in the capping material (61). The barrier (31) can be either partially or fully embedded in the capping layer (61).
摘要翻译：本发明提供了一种在覆盖层（61），下面的介电层（12）和扩散阻挡层（31）的界面处具有改善的机械强度的半导体互连结构。互连结构具有嵌入在封盖材料（61）中的扩散阻挡材料（31）的一部分（41）。阻挡层（31）可以部分或完全嵌入覆盖层（61）中。

6. 发明申请

WO2007044305A2 PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT 审中-公开
标题翻译：包括用于障碍物增强的氧/氮过渡区的种植层
公开(公告)号：WO2007044305A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/038475
申请日：2006-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
发明人： YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
IPC分类号： H01L23/58
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76856 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.
摘要翻译：提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。优选地，互连导电材料是Cu或AlCu。在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

7. 发明申请

WO2010042265A1 DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION 审中-公开
标题翻译：不连续/非均匀金属盖结构和互连整合的过程
公开(公告)号：WO2010042265A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/051226
申请日：2009-07-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GIGNAC, Lynne, M. , HU, Chao-kun , MITTAL, Surbhi , YANG, Chih-chao
发明人： GIGNAC, Lynne, M. , HU, Chao-kun , MITTAL, Surbhi , YANG, Chih-chao
IPC分类号： H01L21/70 , H01L21/00
CPC分类号： H01L23/53238 , H01L21/02362 , H01L21/76849 , H01L21/76865 , H01L21/76868 , H01L23/5283 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.
摘要翻译：提供一种互连结构，其包括至少存在于嵌入在互连电介质材料中的至少一种导电材料的上表面的至少一部分上的含贵金属的盖。在一个实施方案中，含贵金属的帽是不连续的，例如以至少一种导电材料的表面上的核或岛状存在。在另一个实施方案中，含贵金属的盖在至少一种导电材料的表面上具有不均匀的厚度。

8. 发明申请

WO2009139962A2 EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS 审中-公开
标题翻译：电气保险丝应用的有效互连结构
公开(公告)号：WO2009139962A2
公开(公告)日：2009-11-19
申请号：PCT/US2009/038380
申请日：2009-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GIGNAC, Lynne, M. , HU, Chao-kun , YANG, Chih-chao
发明人： GIGNAC, Lynne, M. , HU, Chao-kun , YANG, Chih-chao
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76844 , H01L21/76888 , H01L23/5226 , H01L23/5256 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.
摘要翻译：提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。电介质覆盖层位于电介质材料和导电材料的顶部。在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。因此，当电流提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

9. 发明申请

WO2009097214A1 NOBLE METAL CAP FOR INTERCONNECT STRUCTURES 审中-公开
标题翻译：用于互连结构的NOBLE金属盖
公开(公告)号：WO2009097214A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/031700
申请日：2009-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , EDELSTEIN, Daniel, C. , MCFEELY, Fenton, R.
发明人： YANG, Chih-chao , EDELSTEIN, Daniel, C. , MCFEELY, Fenton, R.
IPC分类号： H01L21/44
CPC分类号： H01L21/76826 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a dielectric material (52) having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material (60) having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic (52B) prior to the formation of the noble metal cap (62). The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.
摘要翻译：提供了包括介电常数为约3.0或更小的电介质材料（52）的互连结构。该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料（60）。电介质材料还具有在形成贵金属帽（62）之前被制成疏水性（52B）的表面层。贵金属盖直接位于至少一个导电材料的上表面上。由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物沉积形式在该疏水电介质表面上。

10. 发明申请

WO2014130129A1 FINFETS AND FIN ISOLATION STRUCTURES 审中-公开
标题翻译： FINFETS和FIN隔离结构
公开(公告)号：WO2014130129A1
公开(公告)日：2014-08-28
申请号：PCT/US2013/073336
申请日：2013-12-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BERGENDAHL, Marc, A. , HORAK, David, V. , KOBURGER, Charles, W., III , PONOTH, Shom , YANG, Chih-chao
IPC分类号： H01L21/8234
CPC分类号： H01L29/0653 , H01L21/32 , H01L21/76205 , H01L21/76229 , H01L21/823431 , H01L21/823481 , H01L21/845 , H01L27/1207 , H01L27/1211
摘要： FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures.
摘要翻译：公开了FinFET和鳍式隔离结构及其制造方法。该方法包括图案化大块基板以形成第一维度和第二维度的多个翅片结构。该方法包括在第一维度和第二维度的多个翅片结构之间的空间中形成氧化物材料。该方法包括在第一尺寸和第二尺寸的翅片结构的选定的侧壁的侧壁上形成封盖材料。该方法包括使氧化物材料凹陷以在封盖材料下方的侧壁上露出本体衬底。该方法包括进行氧化处理以在绝缘鳍结构和具有浇口的散装鳍结构上形成硅。该方法还包括在SOI鳍结构和散装鳍结构上形成栅极结构。

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