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1. 发明专利

JP2005346689A Start of secure kernel in multiprocessor system 有权
标题翻译：多处理器系统中的安全开关
公开(公告)号：JP2005346689A
公开(公告)日：2005-12-15
申请号：JP2004259781
申请日：2004-09-07
申请人： Intel Corp , インテルコーポレイション
发明人： WILSON JOHN H , SCHOINAS IOANNIS T , YOUSIF MAZIN S , RANKIN LINDA J , GRAWROCK DAVID W , GREINER ROBERT J , SUTTON JAMES A , VAID KUSHAGRA , WISEMAN WILLARD M
IPC分类号： G06F21/24 , G06F1/00 , G06F9/445 , G06F9/46 , G06F12/14 , G06F15/163 , G06F15/177 , H04L9/00
CPC分类号： G06F21/575 , G06F21/44 , G06F21/445 , G06F21/50 , G06F21/606 , G06F21/64 , G06F21/71 , G06F2221/034
摘要： PROBLEM TO BE SOLVED: To start a reliable environment in a system. SOLUTION: In one embodiment, this method include steps for: authenticating a start logic processor of the system; evaluating a reliable agent by the start logic processor when the start logic processor is authenticated; and starting the reliable agent by a plurality of processors of the system when the reliable agent is evaluated. In a prescribed embodiment, after the execution of the reliable agent, a secure kernel can be started. For example, the system can be a multiprocessor server system having partially or perfectly connected topology having arbitrary point-to-point interconnection. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在系统中启动可靠的环境。解决方案：在一个实施例中，该方法包括以下步骤：验证系统的起始逻辑处理器; 当开始逻辑处理器被认证时由起始逻辑处理器评估可靠代理; 以及当评估可靠代理时，由系统的多个处理器启动可靠代理。在规定的实施例中，在执行可靠代理之后，可以启动安全内核。例如，该系统可以是具有具有任意点对点互连的部分或完全连接的拓扑的多处理器服务器系统。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2011044161A Transaction based shared data operations in multiprocessor environment 有权
标题翻译：多处理器环境中基于交易的共享数据操作
公开(公告)号：JP2011044161A
公开(公告)日：2011-03-03
申请号：JP2010217663
申请日：2010-09-28
申请人： Intel Corp , インテル・コーポレーション
发明人： KOTTAPALLI SAILESH , CRAWFORD JOHN H , VAID KUSHAGRA
IPC分类号： G06F9/52
CPC分类号： G06F9/528 , G06F9/3834 , G06F9/544
摘要： PROBLEM TO BE SOLVED: To prevent false contention and serialized execution which may be posed because a capability for executing a plurality of software threads is constantly increasing.
SOLUTION: The apparatus and method are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transactional buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止由于执行多个软件线程的能力不断增加而可能引起的错误争用和序列化执行。解决方案：该设备和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。在软件中划分的事务被推测执行。在执行期间，无效的远程访问/请求被加载到并被写入共享存储器的地址由事务缓冲器跟踪。如果遇到无效访问，则重新执行该事务。在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011028774A Transaction-based shared data operation in multiprocessor environment 有权
标题翻译：多处理器环境中基于事务的共享数据操作
公开(公告)号：JP2011028774A
公开(公告)日：2011-02-10
申请号：JP2010217662
申请日：2010-09-28
申请人： Intel Corp , インテル・コーポレーション
发明人： KOTTAPALLI SAILESH , CRAWFORD JOHN H , VAID KUSHAGRA
IPC分类号： G06F9/52 , G06F12/08
CPC分类号： G06F9/528 , G06F9/3834 , G06F9/544
摘要： PROBLEM TO BE SOLVED: To handle shared memory accesses between a plurality of processors, using lock-free synchronization through transactional execution. SOLUTION: A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to share memory are tracked by a transactional buffer (605). If an invalidating access is encountered, the transaction is re-executed (610). After a pre-determined number of times re-executing the transaction (615), the transaction may be re-executed non-speculatively with locks/semaphores (620). COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：处理多个处理器之间的共享存储器访问，通过事务执行使用无锁定同步。
解决方案：在软件中划分的事务被推测执行。在执行期间无效远程访问/请求到由共享存储器加载并被写入共享存储器的地址由事务缓冲器（605）跟踪。如果遇到无效访问，则重新执行事务（610）。在重新执行事务（615）的预定次数之后，可以非推测地用锁/信号量重新执行事务（620）。版权所有（C）2011，JPO＆INPIT

4. 发明申请

WO2004046920A2 PROCESSOR CACHE MEMORY AS RAM FOR EXECUTION OF BOOT CODE 审中-公开
标题翻译：处理器缓存内存作为执行引擎代码的RAM
公开(公告)号：WO2004046920A2
公开(公告)日：2004-06-03
申请号：PCT/US0334808
申请日：2003-10-30
申请人： INTEL CORP
发明人： DATTA SHAM , ZIMMER VINCENT , VAID KUSHAGRA , STEVENS WILLIAM , SANTONI AMY
IPC分类号： G06F9/445 , G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F9/4403 , G06F12/0862 , G06F2212/2515
摘要： In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
摘要翻译：在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

5. 发明专利

DE102005014462B4 Verfahren zum Starten eines sicheren Kernels in einem System 未知
公开(公告)号：DE102005014462B4
公开(公告)日：2013-01-17
申请号：DE102005014462
申请日：2005-03-30
申请人： INTEL CORP
发明人： WILSON JOHN H , SCHOINAS IOANNIS T , YOUSIF MAZIN S , RANKIN LINDA J , GRAWROCK DAVID W , GREINER ROBERT J , SUTTON JAMES A , VAID KUSHAGRA , WISEMAN WILLARD M
IPC分类号： G06F9/445 , G06F21/24 , G06F1/00 , G06F9/46 , G06F12/14 , G06F15/163 , G06F15/177 , H04L9/00
摘要： Verfahren zum Starten eines sicheren Kernels in einem System mit einer teilweise oder einer vollständig verbundenen Topologie, das System eine Mehrzahl von Knoten aufweist und jeder Knoten eine Mehrzahl von Prozessoren enthält; umfassend Laden eines Trusted Agents und eines sicheren Kernels in eine sichere Speichereinrichtung, die in dem System vorgesehen ist, wobei die sichere Speichereinrichtung für jeden der Knoten zugänglich ist, und Initiieren eines sicheren Starts auf einem bestimmten Prozessor, der in einem bestimmten Knoten enthalten ist, Konstruieren eines Spannbaums durch den bestimmten Prozessor, wobei der Spannbaum alle anderen Knoten des Systems in Bezug auf den bestimmten Knoten in einer Mehrzahl von Stufen einer Baumstruktur identifiziert; Senden einer sicheren Startmeldung an den anderen Knoten, der in dem Spannbaum identifiziert ist, durch den bestimmten Prozessor; als Antwort auf die sichere Startmeldung von dem anderen Knoten Validieren des in die sichere Speichereinrichtung geladenen Trusted Agents durch den bestimmten...

6. 发明专利

GB2451200A Data processing apparatus with a storage element coupled to a shared memory, which is biased against receiving new data during a transaction. 未知
公开(公告)号：GB2451200A
公开(公告)日：2009-01-21
申请号：GB0818238
申请日：2005-12-23
申请人： INTEL CORP
发明人： CRAWFORD JOHN H , VAID KUSHAGRA , KOTTAPALLI SAILESH
IPC分类号： G06F9/38 , G06F12/08 , G06F9/46
摘要： Disclosed is a multiprocessor core or multi threaded processor, consisting of logic for executing transactions, a shared memory to hold an input data element used by the transaction, a storage element coupled to the logic and the shared memory, a transaction buffer and logic to abort the transaction. The storage element is biased against receiving new data elements during the pendancy of the transaction. The transaction buffer tracks invaliding requests to the shared memory during the execution of the transaction. The transaction abort logic aborts the transaction in response to the transaction buffer tracking an invaliding request during the execution of the transaction. The apparatus may have a second storage element to hold a locking predicate value. When set to a locked value the execution logic is to execute the transaction non-speculatively using a semaphore to provide exclusive access to the data element in the shred memory. The execution logic may evaluate the count variable in response to aborting the transaction and set the locking predicate to the locking value, if the count variable represents that the transaction has been re-executed a predetermined number of times.

7. 发明专利

GB2429555A Launching a trusted agent using a spanning tree 未知
公开(公告)号：GB2429555A
公开(公告)日：2007-02-28
申请号：GB0620519
申请日：2004-09-23
申请人： INTEL CORP
发明人： WILSON JOHN H , SCHOINAS IOANNIS T , YOUSIF MAZIN S , RANKIN LINDA J , GRAWROCK DAVID W , GREINER ROBERT J , SUTTON JAMES A , VAID KUSHAGRA , WISEMAN WILLARD M
IPC分类号： G06F21/00 , G06F21/24 , G06F1/00 , G06F9/445 , G06F9/46 , G06F12/14 , G06F15/163 , G06F15/177 , G06F15/80 , H04L9/00
摘要： An initial logical processor is used to construct a spanning tree (300) across a plurality of processors (212), and the spanning tree (300) is used to launch a trusted agent on the processor.

8. 发明专利

GB2437211B Transaction based shared data operation in a multiprocessor environment 未知
公开(公告)号：GB2437211B
公开(公告)日：2008-11-19
申请号：GB0714433
申请日：2005-12-23
申请人： INTEL CORP
发明人： KOTTAPALLI SAILESH , CRAWFORD JOHN H , VAID KUSHAGRA
IPC分类号： G06F9/52 , G06F9/46
摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

9. 发明专利

DE112005003339T5 未知
公开(公告)号：DE112005003339T5
公开(公告)日：2007-11-22
申请号：DE112005003339
申请日：2005-12-23
申请人： INTEL CORP
发明人： KOTTAPALLI SAILESH , CRAWFORD JOHN H , VAID KUSHAGRA
IPC分类号： G06F9/52 , G06F9/46
摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

10. 发明专利

GB2414823B Launching a secure kernel in a multiprocessor system 未知
公开(公告)号：GB2414823B
公开(公告)日：2007-04-11
申请号：GB0421213
申请日：2004-09-23
申请人： INTEL CORP
发明人： WILSON JOHN H , SCHOINAS IOANNIS T , YOUSIF MAZIN S , RANKIN LINDA J , GRAWROCK DAVID W , GREINER ROBERT J , SUTTON JAMES A , VAID KUSHAGRA , WISEMAN WILLARD M
IPC分类号： G06F1/00 , G06F21/24 , G06F9/445 , G06F9/46 , G06F12/14 , G06F15/163 , G06F15/177 , H04L9/00

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