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    • 2. 发明申请
    • Template Matching for Resilience and Security Characteristics of Sub-Component Chip Designs
    • 子组件芯片设计的弹性和安全特性的模板匹配
    • US20160154921A1
    • 2016-06-02
    • US14146770
    • 2014-01-03
    • International Business Machines Corporation
    • Eli ArbelPradip BosePrabhakar KudvaShiri MoranK. Paul Muller
    • G06F17/50
    • G06F17/5081
    • A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.
    • 提供了一种用于验证子组件芯片设计的整体弹性和安全特性的机制。 对于识别为出现在子部件芯片设计的设计网表中的弹性模板的每个实例,从而形成一个或多个所识别的弹性部分,确定输出错误信号的设计网表的输出是否互连 到设计网表的一个或多个标识的弹性部分。 响应于与输出错误信号的设计网表的输出相互连接的一个或多个所识别的弹性部分,一个或多个所识别的弹性部分被标记为受到误差信号的保护。 一个或多个所识别的弹性部分的识别和保护一个或多个所识别的弹性部分的误差信号的识别被输出到设计团队。
    • 9. 发明授权
    • Template matching for resilience and security characteristics of sub-component chip designs
    • 子元件芯片设计的弹性和安全特性的模板匹配
    • US09569582B2
    • 2017-02-14
    • US14146770
    • 2014-01-03
    • International Business Machines Corporation
    • Eli ArbelPradip BosePrabhakar KudvaShiri MoranK. Paul Muller
    • G06F17/50
    • G06F17/5081
    • A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.
    • 提供了一种用于验证子组件芯片设计的整体弹性和安全特性的机制。 对于标识为出现在子部件芯片设计的设计网表中的弹性模板的每个实例,从而形成一个或多个所识别的弹性部分,确定输出错误信号的设计网表的输出是否互连 到设计网表的一个或多个标识的弹性部分。 响应于与输出错误信号的设计网表的输出相互连接的一个或多个所识别的弹性部分,一个或多个所识别的弹性部分被标记为受到误差信号的保护。 一个或多个所识别的弹性部分的识别和保护一个或多个所识别的弹性部分的误差信号的识别被输出到设计团队。