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1. 发明申请

WO2018125080A1 ENABLING LONG INTERCONNECT BRIDGES 审中-公开
公开(公告)号：WO2018125080A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068876
申请日：2016-12-28
申请人： INTEL CORPORATION , MAHAJAN, Ravindranath V. , QIAN, Zhiguo , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
发明人： MAHAJAN, Ravindranath V. , BRAUNISCH, Henning , AYGUN, Kemal , SHARAN, Sujit
IPC分类号： H01L23/00 , H01L23/522
摘要： A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

2. 发明申请

WO2017111959A1 PROJECTING CONTACTS AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：投影联系人和制作方法
公开(公告)号：WO2017111959A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067468
申请日：2015-12-22
申请人： INTEL CORPORATION , KIM, Dae-Woo , SHARAN, Sujit , MAHAJAN, Ravindranath, V.
发明人： KIM, Dae-Woo , SHARAN, Sujit , MAHAJAN, Ravindranath, V.
IPC分类号： H01L29/40 , H01L25/03 , H01L29/66
CPC分类号： H01L23/585 , H01L29/40 , H01L29/66
摘要： A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.
摘要翻译：封装组件包括从第一衬底端延伸到第二衬底端的衬底。多个导电迹线沿着衬底延伸。多个触点与多个导电迹线的各个导电迹线耦合。多个接触件中的每一个接触件包括与多个导电迹线中的相应导电迹线耦合的接触焊盘以及与接触焊盘耦接的接触柱，接触柱从接触焊盘延伸。封装覆盖层耦合在多个接触柱上。多个接触柱被配置为穿透封装覆盖层并延伸到封装覆盖层上方的凸起位置。

3. 发明申请

WO2017074390A1 ALTERNATIVE SURFACES FOR CONDUCTIVE PAD LAYERS OF SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：用于半导体封装的硅桥导电垫层的替代表面
公开(公告)号：WO2017074390A1
公开(公告)日：2017-05-04
申请号：PCT/US2015/058069
申请日：2015-10-29
申请人： INTEL CORPORATION
发明人： KIM, Dae-Woo , SHARAN, Sujit
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/48 , H01L23/49822 , H01L2224/14 , H01L2224/16225
摘要： Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.
摘要翻译：描述了用于半导体封装的硅桥的导电焊盘层的替代表面以及所得到的硅桥和半导体封装。在一个示例中，半导体结构包括其上设置有下绝缘层的衬底。基材具有周边。金属化结构设置在下绝缘层上。该金属化结构包括设置在介电材料堆叠中的导电路径。第一和第二多个导电焊盘设置在金属化结构上方的平面中。金属化结构的导电布线将第一多个导电焊盘与第二多个导电焊盘电连接。上绝缘层设置在第一和第二多个导电焊盘上。上绝缘层的周边与衬底的周边基本相同。

4. 发明申请

WO2005034214A2 PROTECTIVE LAYER DURING SCRIBING 审中-公开
标题翻译：保护层在切割期间
公开(公告)号：WO2005034214A2
公开(公告)日：2005-04-14
申请号：PCT/US2004/032458
申请日：2004-09-29
申请人： INTEL CORPORATION , SHARAN, Sujit , DEBONIS, Thomas
发明人： SHARAN, Sujit , DEBONIS, Thomas
IPC分类号： H01L21/00
CPC分类号： H05K3/0029 , H01L21/3043 , H01L21/78 , H05K3/0052 , H05K2201/10977 , H05K2203/0769 , H05K2203/1383
摘要： A method including forming a chemically soluble coating on a plurality exposed contacts on a surface of a circuit substrate; scribing the surface of the substrate along scribe areas; and after scribing, removing a portion of the coating. A method including forming a circuit structure comprises a plurality of exposed contacts on a surface, a location of the exposed contacts defined by a plurality of scribe streets; forming a coating comprising a chemically soluble material on the exposed contacts; scribing the surface of the substrate along the scribe streets; and after scribing, removing the coating. A method including coating a surface of a circuit substrate comprising a plurality of exposed contacts with a chemically soluble material; scribing the surface of the substrate along scribe areas; removing the coating; and sawing the substrate in the scribe areas.
摘要翻译：包括在电路基板的表面上的多个暴露的触点上形成化学可溶涂层的方法; 沿着划线区划划基板的表面; 并在划片后，去除一部分涂层。一种包括形成电路结构的方法包括：在表面上的多个暴露的触点，暴露的触点的位置由多个划道限定; 在暴露的触点上形成包含化学可溶材料的涂层; 沿划线道划线基板的表面; 划片后，去除涂层。一种方法，包括用化学可溶材料涂布包括多个暴露的接触的电路衬底的表面; 沿着划线区划划基板的表面; 去除涂层; 并在切割区域切割基板。

5. 发明申请

WO2022108647A1 HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES 审中-公开
公开(公告)号：WO2022108647A1
公开(公告)日：2022-05-27
申请号：PCT/US2021/049666
申请日：2021-09-09
申请人： INTEL CORPORATION
发明人： PIETAMBARAM, Srinivas V. , MARIN, Brandon C. , PAITAL, Sameer , VADLIMANI, Sai , MANEPALLI, Rahul N. , LI, Xiaoqian , POTHUKUCHI, Suresh V. , SHARAN, Sujit , SARKAR, Arnab , KARHADE, Omkar , DESHPANDE, Nitin , PRATAP, Divya , ECTON, Jeremy , MALLIK, Debendra , MAHAJAN, Ravindranath V. , ZHANG, Zhichao , AYGÜN, Kemal , NIE, Bai , DARMAWIKARTA, Kristof , JAUSSI, James E. , GAMBA, Jason M. , CASPER, Bryan K. , DUAN, Gang , INTI, Rajesh , MANSURI, Mozhgan , JADHAV, Susheel , BROWN, Kenneth , AGRAWAL, Ankar , DOBRIYAL, Priyanka
IPC分类号： G02B6/42 , H01L31/0203 , H01L23/538 , H01L25/16
摘要： Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

6. 发明申请

WO2018034654A1 ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION 审中-公开
标题翻译：圆形金属痕迹削减应力
公开(公告)号：WO2018034654A1
公开(公告)日：2018-02-22
申请号：PCT/US2016/047216
申请日：2016-08-16
申请人： INTEL CORPORATION
发明人： KIM, Dae-Woo , JAIN, Ajay , PATEL, Neha M. , HENDRICKS, Rodrick J. , SHARAN, Sujit
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065
CPC分类号： H01L24/16 , H01L23/538 , H01L23/5383 , H01L23/562 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192 , H01L2924/3512
摘要： An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.
摘要翻译：公开了一种集成电路封装。集成电路封装包括第一集成电路管芯和第二集成电路管芯。集成电路封装进一步包括衬底，其中第一集成电路管芯和第二集成电路管芯都连接到衬底。衬底包括嵌入衬底内的互连桥，其中互连桥包括至少一个金属迹线部件，其中金属迹线部件包括在金属迹线部件的底部上的圆角。

7. 发明申请

WO2018048443A1 EMIB COPPER LAYER FOR SIGNAL AND POWER ROUTING 审中-公开
标题翻译：用于信号和电源路由的EMIB铜层
公开(公告)号：WO2018048443A1
公开(公告)日：2018-03-15
申请号：PCT/US2016/051320
申请日：2016-09-12
申请人： INTEL CORPORATION
发明人： MEKONNEN, Yidnekachew S. , KIM, Dae-Woo , AYGUN, Kemal , SHARAN, Sujit
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00
CPC分类号： H01L23/5383 , H01L24/16 , H01L25/0655 , H01L2224/16227 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15313
摘要： Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.
摘要翻译：嵌入式多芯片互连桥（EMIB）技术提供了一个桥接芯片，其中EMIB包括多个信号和电源布线层。 EMIB消除了对SIP组装硅中介片所需的TSV的需求。在一个实施例中，EMIB包括至少一个铜焊盘。铜焊盘可以配置成在晶圆减薄期间保护EMIB。铜焊盘可以连接到另一个铜焊盘以提供信号路由，从而增加信号接触密度。铜焊盘可以被配置为向一个或多个连接的管芯提供增加的功率输送。

8. 发明申请

WO2018004686A1 DEVICE, METHOD AND SYSTEM FOR PROVIDING RECESSED INTERCONNECT STRUCTURES OF A SUBSTRATE 审中-公开
标题翻译：用于提供衬底的凹陷互连结构的装置，方法和系统
公开(公告)号：WO2018004686A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040832
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LOO, Howe Yin , SHARAN, Sujit , CHUAH, Tin Poay , PRABHAKUMAR, Ananth
IPC分类号： H01L23/538 , H01L23/498 , H01L23/525 , H01L23/00 , H01L25/065
摘要： Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.
摘要翻译：通过衬底促进电路组件之间连接的技术和机制。在一个实施例中，微电子器件包括衬底，其中凹陷区从衬底的第一侧延伸并且仅部分地朝向衬底的第二侧延伸。第一硬件接口的第一输入/输出（IO）触点被设置在凹陷区域中。第一IO触点各自耦合到衬底的相应金属化层，其中凹陷区延伸穿过衬底的一个或多个其他金属化层。在另一个实施例中，微电子器件还包括第二硬件接口的第二IO触点，第二IO触点将微电子器件耦合到印刷电路板。

9. 发明申请

WO2017083010A1 MAGNETIC ALIGNMENT FOR FLIP CHIP MICROELECTRONIC DEVICES 审中-公开
标题翻译：翻转芯片微电子器件的磁性调整
公开(公告)号：WO2017083010A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/052819
申请日：2016-09-21
申请人： INTEL CORPORATION
发明人： AGRAWAL, Ankur , MOOLA, Srinivas , SHARAN, Sujit , GOVINDARAJAN, Vijay
IPC分类号： H01L23/522 , H01L23/498 , H01L23/00 , H01L23/525 , H01F41/04
CPC分类号： H01L23/49838 , H01L21/4846 , H01L23/02 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L23/544 , H01L23/564 , H01L24/16 , H01L24/81 , H01L2223/54426 , H01L2223/54473 , H01L2224/0401 , H01L2224/10135 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2924/01028 , H01L2924/15311 , H01L2924/00014 , H01L2924/014
摘要： Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.
摘要翻译：将至少一个磁性对准结构结合到微电子器件上并且将至少一个对准线圈结合到微电子衬底内，其中对准线圈可以被供电以形成磁场以吸引磁性对准结构，从而将微电子器件对准微电子衬底。在对准之后，微电子器件可以电连接到衬底。实施例可以包括将对准检测线圈额外地结合在微电子衬底内，其中对准检测线圈可以被供电以形成磁场以检测由对准线圈产生的磁场的变化，以便验证微电子器件与微电子基片。

10. 发明申请

WO2017074392A1 METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：用于半导体封装的硅桥的无金属框架设计
公开(公告)号：WO2017074392A1
公开(公告)日：2017-05-04
申请号：PCT/US2015/058074
申请日：2015-10-29
申请人： INTEL CORPORATION
发明人： KIM, Dae-Woo , SHARAN, Sujit , AGRAHARAM, Sairam
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/49827 , H01L22/32 , H01L23/544 , H01L23/585 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L25/18 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/04105 , H01L2224/12105 , H01L2224/14 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81132 , H01L2224/81203 , H01L2224/92125 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/15192 , H01L2924/15313 , H01L2924/3512 , H01L2924/00
摘要： Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
摘要翻译：描述了用于半导体封装的硅桥和所得硅桥和半导体封装的无金属框架设计。在一个示例中，半导体结构包括其上设置有绝缘层的衬底，衬底具有周边。金属化结构设置在绝缘层上，金属化结构包括设置在电介质材料堆叠中的导电布线。第一金属保护环设置在介电材料堆叠中并且围绕导电布线。第二金属保护环设置在介电材料堆叠中并围绕第一金属保护环。介电材料堆叠的无金属区域围绕第二金属保护环。不含金属的区域与第二金属保护环相邻并靠近衬底的周边设置。

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