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1. 发明申请

WO2021257111A1 SWITCH-MANAGED RESOURCE ALLOCATION AND SOFTWARE EXECUTION 审中-公开
公开(公告)号：WO2021257111A1
公开(公告)日：2021-12-23
申请号：PCT/US2020/064670
申请日：2020-12-11
申请人： INTEL CORPORATION
发明人： CONNOR, Patrick , HEARN, James R. , LIEDTKE, Kevin , DUBAL, Scott P.
IPC分类号： H04L12/931 , G06F9/455 , H04L12/803 , H04L12/823 , H04L29/08 , H04L29/06 , G06F2009/4557 , G06F2009/45583 , G06F2009/45595 , G06F9/45558 , H04L12/4645 , H04L47/125 , H04L47/32 , H04L49/356 , H04L63/0227 , H04L63/0272 , H04L63/1408 , H04L63/166 , H04L67/02 , H04L67/1097 , H04L67/34 , H04L69/161 , H04L69/22
摘要： Examples described herein relate to a switch device for a rack of two or more physical servers, wherein the switch device is coupled to the two or more physical servers and the switch device performs packet protocol processing termination for received packets and provides payload data from the received packets without a received packet header to a destination buffer of a destination physical server in the rack. In some examples, the switch device comprises at least one central processing unit, the at least one central processing unit is to execute packet processing operations on the received packets. In some examples, a physical server executes at least one virtualized execution environments (VEE) and the at least one central processing unit executes a VEE for packet processing of packets with data to be accessed by the physical server that executes the VEE.

2. 发明申请

WO2017095503A1 DIRECT MEMORY ACCESS FOR ENDPOINT DEVICES 审中-公开
标题翻译：用于终端设备的直接存储器访问
公开(公告)号：WO2017095503A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/052403
申请日：2016-09-19
申请人： INTEL CORPORATION
发明人： TAMIR, Eliezer , CONNOR, Patrick
IPC分类号： G06F15/16
CPC分类号： H04L67/1097 , H04L45/745 , H04L69/12
摘要： Embodiments of the disclosure are directed to controlling an endpoint device running an endpoint device using a central control server. The central controller server is configured to communicate with the endpoint device across a communications interface compliant with a remote direct access (RDMA) compliant protocol. The central control server includes an RDMA network interface controller and a control process. The control process can execute an endpoint device algorithm to identify read and write commands to be sent across the RDMA protocol-compliant interface to the endpoint device. The RDMA network interface controller can convert messages into RDMA compliant messages that include direct read or write commands and memory location information. The endpoint device can also include a network interface controller that can understand the RDMA message, identify the memory location from the message, and execute the direct read or write access command.
摘要翻译：本公开的实施例针对使用中央控制服务器来控制运行端点设备的端点设备。中央控制器服务器被配置为通过符合远程直接访问（RDMA）兼容协议的通信接口与端点设备进行通信。中央控制服务器包括RDMA网络接口控制器和控制过程。控制过程可以执行端点设备算法以识别要通过RDMA协议兼容接口发送到端点设备的读取和写入命令。 RDMA网络接口控制器可以将消息转换为符合RDMA的消息，其中包括直接读取或写入命令以及内存位置信息。端点设备还可以包括网络接口控制器，该控制器可以理解RDMA消息，从消息中识别存储器位置，并执行直接读取或写入访问命令。

3. 发明申请

WO2017052910A1 REAL-TIME LOCAL AND GLOBAL DATACENTER NETWORK OPTIMIZATIONS BASED ON PLATFORM TELEMETRY DATA 审中-公开
标题翻译：基于平台电视数据的实时局部和全球数字网络优化
公开(公告)号：WO2017052910A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048260
申请日：2016-08-24
申请人： INTEL CORPORATION
发明人： HEARN, James Robert , CONNOR, Patrick , SOOD, Kapil , DUBAL, Scott P. , HERDRICH, Andrew J.
IPC分类号： G06F9/50 , G06F9/455
CPC分类号： G06F9/5011 , G06F9/4881 , G06F9/5027 , G06F13/362 , G06F2209/502 , Y02D10/14 , Y02D10/22
摘要： In one embodiment, a system comprises platform logic comprising a plurality of processor cores and resource allocation logic. The resource allocation logic may receive a processing request and direct the processing request to a processor core of the plurality of processor cores, wherein the processor core is selected based at least in part on telemetry data associated with the platform logic, the telemetry data indicating a topology of at least a portion of the platform logic.
摘要翻译：在一个实施例中，系统包括平台逻辑，其包括多个处理器核心和资源分配逻辑。资源分配逻辑可以接收处理请求并将处理请求引导到多个处理器核心的处理器核心，其中至少部分地基于与平台逻辑相关联的遥测数据来选择处理器核心，所述遥测数据指示平台逻辑的至少一部分的拓扑。

4. 发明申请

WO2015199840A1 APPARATUS AND METHOD FOR USING CONDUCTIVE ADHESIVE FIBERS AS A DATA INTERFACE 审中-公开
标题翻译：使用导电胶粘剂作为数据接口的装置和方法
公开(公告)号：WO2015199840A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/031321
申请日：2015-05-18
申请人： INTEL CORPORATION
发明人： DUBAL, Scott P. , BOOM, Douglas D. , CONNOR, Patrick , PAVLAS, Chris
IPC分类号： G06F13/14
CPC分类号： H01R13/20 , A41D1/005
摘要： An apparatus and method for using conductive adhesive fibers as a data interface are disclosed. A particular embodiment includes: a first array of conductive adhesive fiber fastener pads configured for attachment to a first item; a second array of conductive adhesive fiber fastener pads configured for attachment to a second item, each pad of the first and second array being fabricated with a hook or loop removable fastener, each removable fastener being electrically conductive, the first array of pads being arranged to align with the second array of pads to create a plurality of independent electrical connections when the first item is removably attached to the second item, the plurality of independent electrical connections establishing a data interface connection between the first item and the second item.
摘要翻译：公开了一种使用导电粘合纤维作为数据接口的设备和方法。一个具体实施例包括：第一导电粘合纤维紧固垫片阵列，其被配置用于附接到第一物品; 导电粘合纤维紧固垫的第二阵列，其被配置用于附接到第二物品，所述第一和第二阵列的每个衬垫由钩或环可移除的紧固件制成，每个可移除的紧固件是导电的，所述第一衬垫阵列布置成当第一项目可移除地附接到第二项目时，多个独立的电连接在第一项目和第二项目之间建立数据接口连接，以与第二阵列阵列对准以产生多个独立的电连接。

5. 发明申请

WO2018102086A1 TECHNIQUES FOR A FIELD PROGRAMMABLE GATE ARRAY TO PERFORM A FUNCTION FOR AN APPLICATION SPECIFIC INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2018102086A1
公开(公告)日：2018-06-07
申请号：PCT/US2017/060431
申请日：2017-11-07
申请人： INTEL CORPORATION
发明人： CONNOR, Patrick , DUBAL, Scott P. , SAMUDRALA, Sridhar , MALA, Praveen , LI, Sibai
IPC分类号： G06F13/40 , G06F9/30
CPC分类号： G06F21/76 , G09C1/00 , H04L9/0631 , H04L2209/12 , H04L2209/76
摘要： Examples include techniques for a field programmable gate array (FPGA) to perform one or more functions for an application specific integrated circuit (ASIC). Example techniques include communication between the ASIC and the FPGA via a sideband communication link to enable the ASIC to indicate to the FPGA a need for the FPGA to perform a function to fulfill a request received by the ASIC.

6. 发明申请

WO2011137412A2 PORT TEAMING 审中-公开
标题翻译：港口团队
公开(公告)号：WO2011137412A2
公开(公告)日：2011-11-03
申请号：PCT/US2011/034701
申请日：2011-04-30
申请人： INTEL CORPORATION , JARED, Matthew A. , CONNOR, Patrick
发明人： JARED, Matthew A. , CONNOR, Patrick
IPC分类号： H04L29/10 , H04L29/06
CPC分类号： H04L47/41 , H04L69/14 , Y02D50/30
摘要： An embodiment may include circuitry to be comprised at least in part in a first host, and at least one process to be executed, at least in part, by the circutry. The circuitry may comprise a first port and a second port. The at least one process may detect, at least in part, a first bandwidth condition of the first port, and may associate, at least in part, in response at least in part to the first bandwidth condition, the first port and the second port with a port team. The second port may have been, prior to being associated, at least in part, with the port team, in a relatively lower power state compared to a relatively higher power state. The second port may be in the relatively higher power state after the second port is associated, at least in part, with the port team.
摘要翻译：一个实施例可以包括至少部分地包括在第一主机中的电路以及至少部分由电路执行的至少一个处理。电路可以包括第一端口和第二端口。至少一个进程可以至少部分地检测第一端口的第一带宽条件，并且可以至少部分地至少部分地响应于第一带宽条件来响应第一端口和第二端口与港口团队。在相对较高的功率状态下，第二端口可能在至少部分地与端口组相关联之前处于相对较低的功率状态。在第二端口至少部分地与端口组相关联之后，第二端口可以处于相对较高的功率状态。

7. 发明申请

WO2006124348A2 DMA REORDERING FOR DCA 审中-公开
标题翻译： DCA的DMA追踪
公开(公告)号：WO2006124348A2
公开(公告)日：2006-11-23
申请号：PCT/US2006/017566
申请日：2006-05-02
申请人： INTEL CORPORATION , CONNOR, Patrick , CORNETT, Linden
发明人： CONNOR, Patrick , CORNETT, Linden
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： In an embodiment, an apparatus and method include reordering direct cache access (DCA) and non-DCA transfers so that DCA transfers are last transactions and therefore closer to an interrupt than non-DCA transfers. Embodiments also include coordinating with interrupt processing DCA requests for DCA and non-DCA transfers.
摘要翻译：在一个实施例中，装置和方法包括重新排序直接高速缓存访问（DCA）和非DCA传输，使得DCA传输是最后事务，因此比非DCA传输更接近于中断。实施例还包括协调中断处理对DCA和非DCA传输的DCA请求。

8. 发明申请

WO2005067258A1 METHOD, SYSTEM, AND PROGRAM FOR OVERRUN IDENTIFICATION 审中-公开
标题翻译：方法，系统和程序进行超大规模识别
公开(公告)号：WO2005067258A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043037
申请日：2004-12-20
申请人： INTEL CORPORATION , CONNOR, Patrick
发明人： CONNOR, Patrick
IPC分类号： H04L29/06
CPC分类号： H04L47/29 , H04L47/10 , H04L47/30 , H04L47/32 , H04L49/90 , H04L69/161 , H04L69/163 , H04L69/166
摘要： Provided are a method, system, and program for identifying overrun conditions in data reception, for example. As a receive buffer approaches capacity, received data packets may be truncated to a smaller size. For example, header information may be saved but payload data discarded. The truncated packets may be used to facilitate sending acknowledgments to trigger resending of lost or dropped packets.
摘要翻译：例如，提供了用于识别数据接收中的超限状态的方法，系统和程序。作为接收缓冲器接近容量，接收的数据分组可能被截断为较小的大小。例如，可以保存报头信息，但是丢弃有效载荷数据。截断的分组可以用于促进发送确认以触发丢失或丢弃的分组的重发。

9. 发明申请

WO2021158298A1 OFFLOAD OF STREAMING PROTOCOL PACKET FORMATION 审中-公开
公开(公告)号：WO2021158298A1
公开(公告)日：2021-08-12
申请号：PCT/US2020/065435
申请日：2020-12-16
申请人： INTEL CORPORATION
发明人： CONNOR, Patrick , HEARN, James R. , LIEDTKE, Kevin
IPC分类号： H04L29/06 , H04L12/801 , H04L12/853 , H04L29/08
摘要： Examples described herein relate to providing a streaming protocol packet segmentation offload request to a network interface. The request can specify a segment of content to transmit and meta data associated with the content. The offload request can cause the network interface to generate at least one header field value for the packet and insert at least one header field prior to transmission of the packet. In some examples, the network interface generates a validation value for a transport layer protocol based on the packet with the inserted at least one header field. Some examples provide for pre-packetized content to be stored and available to copy to the network interface. In such examples, the network interface can modify or update certain header fields prior to transmitting the packet.

10. 发明申请

WO2018125490A1 TRANSFERRING PACKETS BETWEEN VIRTUAL MACHINES VIA A DIRECT MEMORY ACCESS DEVICE 审中-公开
公开(公告)号：WO2018125490A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063713
申请日：2017-11-29
申请人： INTEL CORPORATION
发明人： CONNOR, Patrick , DUBAL, Scott P. , TAMIR, Eliezer , PAVLAS, Chris , GASPARAKIS, Iosif , HEARN, James R.
IPC分类号： H04L12/931 , H04L12/861 , H04L12/935
摘要： An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.

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