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1. 发明授权

US09941196B2 Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device 有权
公开(公告)号：US09941196B2
公开(公告)日：2018-04-10
申请号：US15130904
申请日：2016-04-15
申请人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
发明人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
IPC分类号： H01L21/768 , H01L23/498 , H01L23/48 , H01L25/065 , H01L23/525
CPC分类号： H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

2. 发明授权

US09852965B2 Semiconductor devices with through electrodes and methods of fabricating the same 有权
公开(公告)号：US09852965B2
公开(公告)日：2017-12-26
申请号：US15204632
申请日：2016-07-07
申请人： Ho-Jin Lee , Byung Lyul Park , Kwangjin Moon , Jisoon Park , Jin Ho An
发明人： Ho-Jin Lee , Byung Lyul Park , Kwangjin Moon , Jisoon Park , Jin Ho An
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/11 , H01L2224/16145 , H01L2924/181 , H01L2924/00012
摘要： Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

3. 发明授权

US08422600B2 Apparatus and method for estimating phase error based on variable step size 有权
标题翻译：基于可变步长估计相位误差的装置和方法
公开(公告)号：US08422600B2
公开(公告)日：2013-04-16
申请号：US12536856
申请日：2009-08-06
申请人： Pansoo Kim , Dae-Ig Chang , Ho-Jin Lee , Jin-Young Kim , Jae-Sung Park , Young-Sun Lim
发明人： Pansoo Kim , Dae-Ig Chang , Ho-Jin Lee , Jin-Young Kim , Jae-Sung Park , Young-Sun Lim
IPC分类号： H04L27/06 , H03M13/03
CPC分类号： H04L27/22 , H04L1/0047 , H04L1/005 , H04L1/0066 , H04L2027/0067
摘要： Disclosed is a phase error estimating an apparatus and a method which provides improved convergence speed and tracking speed even in mobile channel environment by variably applying the step size for phase error estimation according to channel status. The apparatus for estimating a phase error includes: a posterior probability (APP) average calculating unit for calculating an APP average value from a soft decision result of a currently received symbol; a step size determining unit for determining a step size variably according to channel status; and a phase error estimating unit for estimating a phase error of the currently received symbol from a phase error of a previously received symbol and the APP average value by using the variably determined step size.
摘要翻译：公开了一种相位误差估计装置和方法，即使在移动信道环境中也可以通过根据信道状态可变地应用步长来进行相位误差估计，从而提高收敛速度和跟踪速度。用于估计相位误差的装置包括：后验概率（APP）平均计算单元，用于根据当前接收的符号的软判决结果计算APP平均值; 步长确定单元，用于根据信道状态可变地确定步长; 以及相位误差估计单元，用于通过使用可变确定的步长来估计来自先前接收到的符号的相位误差的当前接收到的符号的相位误差和APP平均值。

4. 发明授权

US08422232B2 System for controlling temperature of antenna module 有权
标题翻译：天线模块温度控制系统
公开(公告)号：US08422232B2
公开(公告)日：2013-04-16
申请号：US13002888
申请日：2009-07-21
申请人： Changsoo Kwak , In-Bok Yom , So-Hyeun Yun , Donghwan Shin , Ho-Jin Lee
发明人： Changsoo Kwak , In-Bok Yom , So-Hyeun Yun , Donghwan Shin , Ho-Jin Lee
IPC分类号： H05K7/20
CPC分类号： H01Q1/02 , H01Q1/42
摘要： A system for controlling temperature of an antenna module including a heat generating module, and a radome and an underbody cover that enclose the heat generating module. The system includes: a heat collecting unit mounted on inner surface of the antenna module; a heat discharging unit mounted on outer surface of the antenna module; and a heat transfer unit for transferring heat from the heat collecting unit to the heat discharging unit.
摘要翻译：一种用于控制包括发热模块的天线模块的温度的系统，以及包围发热模块的天线罩和底盖。该系统包括：安装在天线模块的内表面上的集热单元; 安装在所述天线模块的外表面上的放热单元; 以及用于将热量从集热单元传递到散热单元的传热单元。

5. 发明授权

US08335255B2 Motion estimation method, medium, and system with fast motion estimation 有权
标题翻译：运动估计方法，中等和快速运动估计系统
公开(公告)号：US08335255B2
公开(公告)日：2012-12-18
申请号：US11783599
申请日：2007-04-10
申请人： Ho-Jin Lee , Sang-Jo Lee , Si-hwa Lee , Do-hyung Kim
发明人： Ho-Jin Lee , Sang-Jo Lee , Si-hwa Lee , Do-hyung Kim
IPC分类号： H04N7/12
CPC分类号： H04N19/56 , H04N19/51
摘要： A motion estimation method, medium, and system with fast motion estimation. The motion estimation method includes comparing a cost indicating a difference between a current block of a current image and a block of a reference image specified by a starting point with a predetermined threshold and selectively searching for the best matching block of the current block from the starting point according to the comparison result.
摘要翻译：具有快速运动估计的运动估计方法，介质和系统。运动估计方法包括将当前图像的当前块与由起始点指定的参考图像的块之间的差指定为预定阈值的成本进行比较，并且从开始选择性地搜索当前块的最佳匹配块根据比较结果。

6. 发明申请

US20120091580A1 Semiconductor Devices And Methods Of Fabricating The Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120091580A1
公开(公告)日：2012-04-19
申请号：US13211574
申请日：2011-08-17
申请人： SeYoung Jeong , Hogeon Song , Chungsun Lee , Ho-Jin Lee
发明人： SeYoung Jeong , Hogeon Song , Chungsun Lee , Ho-Jin Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/563 , H01L21/76898 , H01L23/3128 , H01L24/04 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/13009 , H01L2224/13025 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48227 , H01L2224/73257 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06544 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/1304 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19104 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor device. The semiconductor device may include a first semiconductor chip that includes a first through silicon via having a first protrusion height and a second through silicon via having a second protrusion height greater than the first protrusion height which are penetrating at least a portion of the first semiconductor chip, a second semiconductor chip may be electrically connected to the first through silicon via, and a third semiconductor chip may be electrically connected to the second through silicon via.
摘要翻译：提供一种半导体器件。半导体器件可以包括第一半导体芯片，其包括具有第一突起高度的第一至第二硅通孔以及具有大于第一突出高度的第二突出高度的第二穿透硅通孔，该第二突出高度穿过第一半导体芯片的至少一部分，第二半导体芯片可以电连接到第一通孔硅通孔，并且第三半导体芯片可以电连接到第二通孔硅通孔。

7. 发明授权

US08120177B2 Wafer level package having a stress relief spacer and manufacturing method thereof 有权
公开(公告)号：US08120177B2
公开(公告)日：2012-02-21
申请号：US12910260
申请日：2010-10-22
申请人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
发明人： Hyun-Soo Chung , Ho-Jin Lee , Dong-Hyun Jang , Dong-Ho Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/274 , H01L2225/06513 , H01L2225/06541 , H01L2924/01079 , H01L2924/01087
摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

8. 发明授权

US08049319B2 Ultra wideband system-on-package 有权
标题翻译：超宽带系统级封装
公开(公告)号：US08049319B2
公开(公告)日：2011-11-01
申请号：US12604354
申请日：2009-10-22
申请人： In-Kwon Ju , In-Bok Yom , Ho-Jin Lee
发明人： In-Kwon Ju , In-Bok Yom , Ho-Jin Lee
IPC分类号： H01L23/02 , H01L23/053 , H01L23/12 , H01L23/34
CPC分类号： H01L23/66 , H01L23/552 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2224/48091 , H01L2224/73265 , H01L2924/1423 , H01L2924/19032 , H01L2924/19033 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.
摘要翻译：该研究公开了一种超宽带系统级封装（SoP）。 SoP包括一个包装体; 安装在封装主体上的第一集成电路; 连接到第一集成电路的第一信号传输单元; 连接到第一信号传输单元并包括板条线和槽线的信号通路; 以及连接到信号通道的第二信号传输单元。本研究的技术可以通过最小化在向外部电路传输信号的过程中发生的垂直转换期间出现的信号的不连续性来传输超宽带信号及其制造方法。

9. 发明授权

US07995578B2 Repetition apparatus and method for repeatedly transmitting and receiving data packet using different puncturing patterns 失效
标题翻译：用于使用不同的打孔模式重复地发送和接收数据分组的重复装置和方法
公开(公告)号：US07995578B2
公开(公告)日：2011-08-09
申请号：US12334043
申请日：2008-12-12
申请人： Pansoo Kim , In-Ki Lee , Dae-Ig Chang , Ho-Jin Lee , Namshik Kim , Bongseop Song , Hyuncheol Park
发明人： Pansoo Kim , In-Ki Lee , Dae-Ig Chang , Ho-Jin Lee , Namshik Kim , Bongseop Song , Hyuncheol Park
IPC分类号： H04J3/16
CPC分类号： H04L1/0071 , H04L1/0013 , H04L1/0068 , H04L1/08
摘要： Provided are repetition apparatus and method for repeatedly transmitting and receiving a data packet using different puncturing patterns to overcome signal attenuation and fading in a high speed mobile environment by repeatedly transmitting the duplicated information bit sequences with parity bits having a different puncturing pattern after channel-encoding the duplicated information bit. The repetition apparatus for repeatedly transmitting a data packet, includes a dual data generator for generating duplicated information bit sequences identical to each of information bit sequences to transmit, a channel encoder for dividing each of the duplicated information bit sequences into a plurality of information bits, and generating coded data packets alternately having a plurality of parity bits according to different puncturing patterns for each of the divided information bits, and a transmitter for transmitting the generated coded data packets sequentially.
摘要翻译：提供了一种重复装置和方法，用于使用不同的打孔模式重复地发送和接收数据包，以通过在频道编码之后重复地发送具有不同打孔图案的奇偶校验位的复制信息比特序列来克服高速移动环境中的信号衰减和衰落重复的信息位。用于重复发送数据分组的重复装置包括：双数据产生器，用于产生与要发送的每个信息比特序列相同的重复信息比特序列，用于将每个复制信息比特序列分成多个信息比特的信道编码器，以及根据用于每个分割的信息比特的不同的删截图案，交替地生成具有多个奇偶校验位的编码数据分组，以及发送器，用于顺序地发送所生成的编码数据分组。

10. 发明申请

US20110147946A1 WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME 失效
标题翻译： WAFER LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME
公开(公告)号：US20110147946A1
公开(公告)日：2011-06-23
申请号：US13027594
申请日：2011-02-15
申请人： In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
发明人： In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/11462 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/0106 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19043 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
摘要翻译：一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。在集成电路区域上形成第一金属层图案。通孔形成为延伸穿过第一金属层图案和集成电路区域。最终的金属层图案形成在第一金属层图案之上并且在通孔内。在通孔内形成插头。此后，形成钝化层以覆盖最终金属层图案。

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