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1. 发明申请

US20050278668A1 Method of estimating crosstalk noise in lumped RLC coupled interconnects 失效
标题翻译：估计集中RLC耦合互连中串扰噪声的方法
公开(公告)号：US20050278668A1
公开(公告)日：2005-12-15
申请号：US10853854
申请日：2004-05-25
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects is provided. In the invention, high-speed VLSI interconnects are modeled as lumped RLC coupled trees. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.
摘要翻译：提供了一种用于有效估计高速VLSI互连的串扰噪声的方法。在本发明中，高速VLSI互连被建模为集中RLC耦合的树。可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。此外，每个节点的电压矩的分析公式将被明确推导出来。可以有效地实现这些公式用于串扰估计。

2. 发明申请

US20060100831A1 Generalizations of adjoint networks techniques for RLC interconnects model-order reductions 有权
标题翻译：用于RLC互连的伴随网络技术的概括模型级减少
公开(公告)号：US20060100831A1
公开(公告)日：2006-05-11
申请号：US10982668
申请日：2004-11-05
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This paper extends this technique for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposal method.
摘要翻译：伴随网络减少技术已被证明可以减少构造一致性变换矩阵的计算复杂度的50％。该方法适用于分析RLC互连电路的特殊多端口驱动点阻抗。本文对RLC互连的一般情况进行了扩展。还研究了常规方法和提出的方法之间的比较研究。实验结果将表明提案方法的准确性和效率。

3. 发明授权

US07124381B2 Method of estimating crosstalk noise in lumped RLC coupled interconnects 失效
标题翻译：估计集中RLC耦合互连中串扰噪声的方法
公开(公告)号：US07124381B2
公开(公告)日：2006-10-17
申请号：US10853854
申请日：2004-05-25
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects models high-speed VLSI interconnects as lumped RLG coupled frees. An inductive crosstalk noise waveform can be accurately estimated in an efficient manner using a linear time moment computation technique in conjunction with a projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived taking into consideration of both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for use in crosstalk estimations.
摘要翻译：高效VLSI互连的串扰噪声的有效估计方法是将高速VLSI互连模型作为集中的RLG耦合释放模型。可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。考虑到自感和互感两者，导出耦合RC树的力矩计算的递归公式。此外，每个节点的电压矩的分析公式将被明确推导出来。这些公式可以有效地实现用于串扰估计。

4. 发明申请

US20060015832A1 Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops 有权
标题翻译：高速VLSI与电阻环R（L）C互连中的时刻计算方法
公开(公告)号：US20060015832A1
公开(公告)日：2006-01-19
申请号：US10889795
申请日：2004-07-13
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036
摘要： A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results have demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.
摘要翻译：提出了一种具有多个电阻环路的通用集总R（L）C互连电路的新时刻计算技术。集中R（L）C网络使用撕裂概念可以划分为生成树和几个电阻链路。来自每个树的网络时刻的贡献和相应的链接可以独立确定。通过组合常规力矩计算算法和减少二阶决策图（ROBDD），提出的方法可以有效地计算系统时间。实验结果表明，所提出的方法确实可以获得准确的时刻，并且比常规方法更有效。

5. 发明授权

US07797140B2 Generalizations of adjoint networks techniques for RLC interconnects model-order reductions 有权
标题翻译：用于RLC互连的伴随网络技术的概括模型级减少
公开(公告)号：US07797140B2
公开(公告)日：2010-09-14
申请号：US10982668
申请日：2004-11-05
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F7/60 , G06F17/10
CPC分类号： G06F17/5036
摘要： The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This technique is extended for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposed method.
摘要翻译：伴随网络减少技术已被证明可以减少构造一致性变换矩阵的计算复杂度的50％。该方法适用于分析RLC互连电路的特殊多端口驱动点阻抗。对于RLC互连的一般情况，该技术被扩展。还研究了常规方法和提出的方法之间的比较研究。实验结果将证明所提方法的准确性和效率。

6. 发明授权

US07254790B2 Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops 有权
标题翻译：高速VLSI与电阻环R（L）C互连中的时刻计算方法
公开(公告)号：US07254790B2
公开(公告)日：2007-08-07
申请号：US10889795
申请日：2004-07-13
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036
摘要： A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.
摘要翻译：提出了具有多个电阻环路的一般集总R（L）C互连电路的矩计算技术。集中R（L）C网络使用撕裂概念可以划分为生成树和几个电阻链路。每个空闲网络时刻的贡献和相应的链接可以独立确定。通过组合常规力矩计算算法和减少二阶决策图（ROBDD），提出的方法可以有效地计算系统时间。实验结果表明，所提出的方法确实可以获得准确的时刻，并且比常规方法更有效。

7. 发明授权

US07017130B2 Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits 失效
标题翻译：在纳米级集成电路中利用分布式线路耦合的RLC互连中估计串扰噪声的验证方法
公开(公告)号：US07017130B2
公开(公告)日：2006-03-21
申请号：US10889497
申请日：2004-07-12
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.
摘要翻译：提供了一种在纳米级集成电路中与分布式线路连接的RLC互连中估计串扰噪声的方法和验证。在本发明中，纳米VLSI互连被建模为分布式RLC耦合树。可以看出，分布式线路的力矩计算的效率和精度优于集中线路。可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。此外，每个节点的电压矩的分析公式将被明确推导出来。可以有效地实现这些公式用于串扰估计。

8. 发明申请

US20060010406A1 METHOD OF VERIFICATION OF ESTIMATING CROSSTALK NOISE IN COUPLED RLC INTERCONNECTS WITH DISTRIBUTED LINE IN NANOMETER INTEGRATED CIRCUITS 失效
标题翻译：在纳米级集成电路中与分布式线路耦合的RLC互连中估计混合噪声的验证方法
公开(公告)号：US20060010406A1
公开(公告)日：2006-01-12
申请号：US10889497
申请日：2004-07-12
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Ming-Hong Lai
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036
摘要： A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.
摘要翻译：提供了一种在纳米级集成电路中与分布式线路连接的RLC互连中估计串扰噪声的方法和验证。在本发明中，纳米VLSI互连被建模为分布式RLC耦合树。可以看出，分布式线路的力矩计算的效率和精度优于集中线路。可以使用线性时间矩计算技术结合基于投影的顺序降低方法，以有效的方式精确地估计电感串扰噪声波形。考虑自感和互感两种情况，导出耦合RC树的力矩计算的递归公式。此外，每个节点的电压矩的分析公式将被明确推导出来。可以有效地实现这些公式用于串扰估计。

9. 发明授权

US07512525B2 Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders 失效
标题翻译：使用具有自适应顺序的合理Arnoldi方法，VLSI互连的多点模型减少
公开(公告)号：US07512525B2
公开(公告)日：2009-03-31
申请号：US11029587
申请日：2005-01-05
申请人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Chao-Kai Chang
发明人： Herng-Jer Lee , Chia-Chi Chu , Wu-Shiung Feng , Chao-Kai Chang
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.
摘要翻译：利用具有自适应阶数（RAMAO）的合理Arnoldi方法的模型简化方法被应用于高速VLSI互连模型。该方法基于经典多点Pade近似的扩展，使用理性Arnoldi迭代法。给定一组预定的扩展点，首先推导出与每个扩展点相关的原始系统的输出时刻与低阶系统的输出时刻之间的误差的精确表达式。在所提出的RAMAO算法的每次迭代中，将选择对应于最大输出力矩误差的扩展频率。因此，相应的降阶模型在相同阶数的所有降阶模型中产生最大的输出矩的改进。

10. 发明申请

US20070033549A1 Interconnect model-order reduction method 失效
标题翻译：互连模型阶降序法
公开(公告)号：US20070033549A1
公开(公告)日：2007-02-08
申请号：US11199026
申请日：2005-08-08
申请人： Chia-Chi Chu , Herng-Jer Lee , Wu-Shiung Feng , Chao-Kai Chang
发明人： Chia-Chi Chu , Herng-Jer Lee , Wu-Shiung Feng , Chao-Kai Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.
摘要翻译：一种用于通过使用基于迭代的Arnoldi算法来将纳米级半导体互连网络还原为原始互连网络的互连模型级降低方法。该方法基于投影方法进行，并且已经成为有效的互连建模和模拟的必要条件。为了选择可以有效地反映原始互连网络的基本动力学的简化模型的顺序，原始互连网络的传递函数与简化的互连模型之间的残差可能被认为是确定迭代过程应该如何结束，这里得出的残差的解析表达式。此外，还原互连模型的近似传递函数也可以表示为原始互连模型和一些附加扰动的相加。扰动矩阵仅与Arnoldi算法前一步的合成矢量有关。因此，剩余误差信息可以作为Krylov子空间模型顺序算法中使用的顺序选择方案的参考。

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