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1. 发明公开

EP0767500A2 Power semiconductor device with lattice defects 失效
标题翻译：与晶格缺陷的半导体功率器件
公开(公告)号：EP0767500A2
公开(公告)日：1997-04-09
申请号：EP96115659.3
申请日：1996-09-30
申请人： HITACHI, LTD.
发明人： Ishikawa, Katsumi , Saito, Katsuaki , Sato, Yutaka , Watanabe, Atsuo , Katoh, Shuji , Momma, Naohiro
IPC分类号： H01L29/74 , H01L29/32
CPC分类号： H01L29/74 , H01L29/32 , H01L29/861 , Y10S257/913
摘要： In a semiconductor device such as a diode and thyristor having at least one pn junction between a pair of main surfaces, a first main electrode (31, 33) formed on the surface of one of the main surfaces and a second main electrode (32, 34) formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode (31, 33) to the second main electrode (32, 34). Since the distribution of carrier density in conduction state can be flattened according to the invention, the reverse recovery charge can be reduced substantially without causing ON-state voltage to increase.

2. 发明授权

EP0252206B1 Method of fabricating semiconductor structure 失效
标题翻译：制造半导体结构的方法
公开(公告)号：EP0252206B1
公开(公告)日：1992-07-15
申请号：EP87101113.6
申请日：1987-01-27
申请人： HITACHI, LTD.
发明人： Homma, Hideo , Misawa, Yutaka , Momma, Naohiro
IPC分类号： H01L21/82 , H01L21/285 , H01L21/00
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/32137 , H01L21/8249 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/78

3. 发明公开

EP0290036A3 Plasma treatment apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：EP0290036A3
公开(公告)日：1989-11-15
申请号：EP88107319.1
申请日：1988-05-06
申请人： HITACHI, LTD. , HITACHI SERVICE ENGINEERING CO., LTD.
发明人： Mochizuki, Yasuhiro , Momma, Naohiro , Takahashi, Shigeru , Fukuda, Takuya , Suzuki, Noboru , Sonobe, Tadasi , Chiba, Kiyoshi , Suzuki, Kazuo
IPC分类号： H05H1/46 , H01J37/32
CPC分类号： H01J37/32192 , C23C16/511 , H01J37/32678
摘要： A plasma treatment apparatus capable of depositing a desired substance on a substrate (5, 211, 312) to form a thin film is disclosed. Especially, for a plasma treatment apparatus using microwaves, a structure of the apparatus is disclosed with which the film deposition rate and the film quality can be improved and the size of the apparatus can be made small.

4. 发明公开

EP0252206A2 Method of fabricating semiconductor structure 失效
标题翻译： Verfahren zum Herstellen einer Halbleiterstruktur。
公开(公告)号：EP0252206A2
公开(公告)日：1988-01-13
申请号：EP87101113.6
申请日：1987-01-27
申请人： HITACHI, LTD.
发明人： Homma, Hideo , Misawa, Yutaka , Momma, Naohiro
IPC分类号： H01L21/82 , H01L21/285 , H01L21/00
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/32137 , H01L21/8249 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/78
摘要： A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region (51) of a first conductivity type and at least one second semiconductor region (50) of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film (56), an intermediate layer which is a silicon nitride film (57), and a top layer which is a polycrystalline silicon film (58) doped with one of arsenic and phosphorus; forming a first insulating layer (61) on the side wall of the three-layer film; forming a second polycrystalline silicon film (62) on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film (58) into the second polycrystalline silicon film (62); selectively etching off the first polycrystalline silicon film (58) and that portion (62A) of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer (64) at least on the surface of that portion (63A) of the second polycrystalline silicon film which exists on the second semiconductor region (50); removing the silicon nitride film (57) and the conductive film (56) which exist on the second semiconductor region (50), while using the second insulating layer (64) as a mask, to form an aperture and forming a third polycrystalline silicon film (69) so that the aperture (68) is covered by the third polycrystalline silicon film.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体层的主表面中形成至少一个第一导电类型的第一半导体区域（51）和第二导电类型的至少一个第二半导体区域（50）的第一导电类型; 在第一和第二半导体区域中的每一个上形成具有期望形状的三层膜，三层膜由作为导电膜（56）的底层构成，作为氮化硅膜的中间层（57），以及掺杂有砷和磷之一的多晶硅膜（58）的顶层; 在所述三层膜的侧壁上形成第一绝缘层（61）; 在整个表面上形成第二多晶硅膜（62），并将砷和磷中的一种从第一多晶硅膜（58）扩散到第二多晶硅膜（62）中; 选择性地蚀刻出第一多晶硅膜（58）和砷和磷之一已被扩散的第二多晶硅膜的部分（62A）; 至少在所述第二半导体区域（50）上存在的所述第二多晶硅膜的所述部分（63A）的表面上形成第二绝缘层（64）; 在使用第二绝缘层（64）作为掩模的同时，移除存在于第二半导体区域（50）上的氮化硅膜（57）和导电膜（56），以形成孔并形成第三多晶硅膜（69），使得孔（68）被第三多晶硅膜覆盖。

5. 发明授权

EP0222215B1 Polysilicon MOS transistor and method of manufacturing the same 失效
标题翻译：多晶硅MOS晶体管及其制造方法
公开(公告)号：EP0222215B1
公开(公告)日：1991-10-16
申请号：EP86114610.8
申请日：1986-10-22
申请人： HITACHI, LTD.
发明人： Saito, Ryuichi , Momma, Naohiro
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/66757 , H01L21/32155 , H01L27/0922 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/04 , H01L29/167 , H01L29/78618 , H01L29/78675 , H01L29/78684

6. 发明公开

EP0252206A3 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：EP0252206A3
公开(公告)日：1988-08-31
申请号：EP87101113
申请日：1987-01-27
申请人： HITACHI, LTD.
发明人： Homma, Hideo , Misawa, Yutaka , Momma, Naohiro
IPC分类号： H01L21/82 , H01L21/285 , H01L21/00
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/32137 , H01L21/8249 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/78
摘要： A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region (51) of a first conductivity type and at least one second semiconductor region (50) of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film (56), an intermediate layer which is a silicon nitride film (57), and a top layer which is a polycrystalline silicon film (58) doped with one of arsenic and phosphorus; forming a first insulating layer (61) on the side wall of the three-layer film; forming a second polycrystalline silicon film (62) on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film (58) into the second polycrystalline silicon film (62); selectively etching off the first polycrystalline silicon film (58) and that portion (62A) of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer (64) at least on the surface of that portion (63A) of the second polycrystalline silicon film which exists on the second semiconductor region (50); removing the silicon nitride film (57) and the conductive film (56) which exist on the second semiconductor region (50), while using the second insulating layer (64) as a mask, to form an aperture and forming a third polycrystalline silicon film (69) so that the aperture (68) is covered by the third polycrystalline silicon film.

7. 发明公开

EP0222215A2 Polysilicon MOS transistor and method of manufacturing the same 失效
标题翻译：多晶硅MOS晶体管和方法，用于其生产。
公开(公告)号：EP0222215A2
公开(公告)日：1987-05-20
申请号：EP86114610.8
申请日：1986-10-22
申请人： HITACHI, LTD.
发明人： Saito, Ryuichi , Momma, Naohiro
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/66757 , H01L21/32155 , H01L27/0922 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/04 , H01L29/167 , H01L29/78618 , H01L29/78675 , H01L29/78684
摘要： The presend invention relates to a semiconductor device including a MOS transistor which is formed with a source region (6; 6a), a drain region (6; 6a) and a channel region (7) by the use of polycrystalline silicon, and a method of amnufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer (3) over the whole area thereof, and restrain conductive ions in the source and drain regions (6; 6a) from diffusing into the channel region (7).

8. 发明公开

EP0171605A3 Method of manufacturing semiconductor integrated circuit involving an organic film 有权
标题翻译：制造涉及有机膜的半导体集成电路的方法
公开(公告)号：EP0171605A3
公开(公告)日：1986-06-25
申请号：EP85108627
申请日：1985-07-11
申请人： HITACHI, LTD.
发明人： Mochizuki, Yasuhiro , Tsukuda, Kiyoshi , Momma, Naohiro , Hirao, Mitsuru
IPC分类号： H01L21/31 , C23C16/04
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02211 , H01L21/02277 , H01L21/02304 , H01L21/0271 , H01L21/3145 , H01L21/31612
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit wherein a thin film such as insulator film is formed on selected areas of a semiconductor substrate. According to the present invention, photoresist is provided on selected areas of the semiconductor substrate in advance. The semiconductor substrate is placed in a reactor, and raw material gases for the thin film are caused to flow through the reactor, to form the thin film in accordance with chemical vapor deposition utilizing a photochemical reaction and to simultaneously decompose the photoresist owing to a photochemical reaction. Thus, the thin film is deposited on the parts other than the photoresist.

9. 发明公开

EP0767500A3 Power semiconductor device with lattice defects 失效
标题翻译： Halbleiterleistungsbauteil mit Gitterfehlstellen
公开(公告)号：EP0767500A3
公开(公告)日：1999-07-28
申请号：EP96115659.3
申请日：1996-09-30
申请人： HITACHI, LTD.
发明人： Ishikawa, Katsumi , Saito, Katsuaki , Sato, Yutaka , Watanabe, Atsuo , Katoh, Shuji , Momma, Naohiro
IPC分类号： H01L29/74 , H01L29/32
CPC分类号： H01L29/74 , H01L29/32 , H01L29/861 , Y10S257/913
摘要： In a semiconductor device such as a diode and thyristor having at least one pn junction between a pair of main surfaces, a first main electrode (31, 33) formed on the surface of one of the main surfaces and a second main electrode (32, 34) formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode (31, 33) to the second main electrode (32, 34). Since the distribution of carrier density in conduction state can be flattened according to the invention, the reverse recovery charge can be reduced substantially without causing ON-state voltage to increase.
摘要翻译：在诸如二极管和晶闸管的半导体器件中，在一对主表面之间具有至少一个pn结，形成在一个主表面的表面上的第一主电极（31,33）和第二主电极 34）形成在另一个主表面的表面上，形成半导体晶格缺陷，使得其晶格缺陷密度在从第一主电极（31,33）到第二主电极（32,32）的方向上逐渐增加， 34）。由于根据本发明能够使导通状态下的载流子密度分布变平坦，所以可以大大降低反向恢复电荷，而不会导致ON状态电压增加。

10. 发明授权

EP0275965B1 Plasma operation apparatus 失效
标题翻译：随着等离子工作机器。
公开(公告)号：EP0275965B1
公开(公告)日：1995-05-31
申请号：EP88100672.0
申请日：1988-01-19
申请人： HITACHI, LTD. , HITACHI SERVICE ENGINEERING CO., LTD.
发明人： Fukuda, Takuya , Mochizuki, Yasuhiro , Momma, Naohiro , Takahashi, Shigeru , Suzuki, Noboru , Sonobe, Tadasi , Chiba, Kiyosi , Suzuki, Kazuo
IPC分类号： H01J37/32 , C23C16/50 , C23F4/00
CPC分类号： H01J37/32192 , C23C16/511 , H01J37/32678

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