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1. 发明授权

US06748517B1 Constructing database representing manifold array architecture instruction set for use in support tool code creation 有权
标题翻译：构建表示用于支持工具代码创建的多支数组架构指令集的数据库
公开(公告)号：US06748517B1
公开(公告)日：2004-06-08
申请号：US09599980
申请日：2000-06-22
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F944
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，可以以数据库形式表示指令集的相对容易程度，可以创建工具的准备就绪能力，自检代码的准备生成和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

2. 发明申请

US20090063724A1 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US20090063724A1
公开(公告)日：2009-03-05
申请号：US11827548
申请日：2007-07-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

3. 发明授权

US07962667B2 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US07962667B2
公开(公告)日：2011-06-14
申请号：US11827548
申请日：2007-07-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

4. 发明申请

US20130007331A1 System Core for Transferring Data Between an External Device and Memory 失效
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20130007331A1
公开(公告)日：2013-01-03
申请号：US13611969
申请日：2012-09-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/36
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

5. 发明申请

US20110219210A1 System Core for Transferring Data Between an External Device and Memory 失效
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20110219210A1
公开(公告)日：2011-09-08
申请号：US13106042
申请日：2011-05-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

6. 发明授权

US08117357B2 System core for transferring data between an external device and memory 失效
公开(公告)号：US08117357B2
公开(公告)日：2012-02-14
申请号：US13106042
申请日：2011-05-12
申请人： Gerald George Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

7. 发明申请

US20080133892A1 Methods and Apparatus for Initiating and Resynchronizing Multi-Cycle SIMD Instructions 失效
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US20080133892A1
公开(公告)日：2008-06-05
申请号：US11778303
申请日：2007-07-16
申请人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

8. 发明授权

US06622234B1 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 有权
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US06622234B1
公开(公告)日：2003-09-16
申请号：US09598564
申请日：2000-06-21
申请人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单个指令多个数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂的指令及其伴随的多周期执行单元的技术。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

9. 发明授权

US06397324B1 Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file 有权
标题翻译：使用加载和存储地址生成器访问存储库中的表，共享存储与地址寄存器文件分离的计算寄存器文件的读取端口
公开(公告)号：US06397324B1
公开(公告)日：2002-05-28
申请号：US09596103
申请日：2000-06-16
申请人： Edwin Frank Barry , Charles W. Kurak, Jr. , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Charles W. Kurak, Jr. , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9312
CPC分类号： G06F9/3004 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , H03M7/425
摘要： A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers. The present approach provides an efficient mechanism for supporting these functions while maintaining separate compute and address register files.
摘要翻译：由于并行执行包括VLIW的子指令，很长的指令字（VLIW）处理器通常需要大量的寄存器文件端口。通过将通用寄存器文件分割成单独的地址和计算寄存器文件，计算寄存器文件端口的数量大大减少。当支持具有索引寻址模式的多个加载和存储执行单元时，这种减少尤其明显。这意味着在编程模型中实现了更快的寄存器文件和专用地址寄存器。节省成本是为计算寄存器文件和地址寄存器文件之间的数据移动提供支持。此外，地址算术，表查找和存储到表函数是当地址寄存器与计算寄存器分离时不能明显获得的所需函数。本方法提供了一种支持这些功能的有效机制，同时保持单独的计算和地址寄存器文件。

10. 发明申请

US20080222333A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20080222333A1
公开(公告)日：2008-09-11
申请号：US12120543
申请日：2008-05-14
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F13/24 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

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