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1. 发明申请

US20060044166A1 Noise shaper circuit and method for reducing switching noise 有权
标题翻译：噪声整形电路及降低开关噪声的方法
公开(公告)号：US20060044166A1
公开(公告)日：2006-03-02
申请号：US11202636
申请日：2005-08-11
申请人： Florian Pfister , Dieter Luecking , Matthias Vierthaler , Carsten Noeske
发明人： Florian Pfister , Dieter Luecking , Matthias Vierthaler , Carsten Noeske
IPC分类号： H03M3/00
CPC分类号： H03M7/3006 , H03M7/3042
摘要： Noise that is normally generated during the switching of a noise shaper may be reduced by switching the noise shaper to an inactive or off state after the occurrence of one or more predetermined criteria, for example the detection of a predetermined number of data values below a threshold value or equal to a certain value, or of a predetermined number of data values within a threshold region about a value that is constant with respect to the data values.
摘要翻译：在噪声整形器的切换期间通常产生的噪声可以通过在发生一个或多个预定标准之后将噪声整形器切换到无效或断开状态来减少，例如，检测到低于阈值的预定数量的数据值值或等于某个值，或者阈值区域内的预定数量的数据值关于相对于数据值是恒定的值。

2. 发明授权

US07233271B2 Noise shaper circuit and method for reducing switching noise 有权
标题翻译：噪声整形电路及降低开关噪声的方法
公开(公告)号：US07233271B2
公开(公告)日：2007-06-19
申请号：US11202636
申请日：2005-08-11
申请人： Florian Pfister , Dieter Luecking , Matthias Vierthaler , Carsten Noeske
发明人： Florian Pfister , Dieter Luecking , Matthias Vierthaler , Carsten Noeske
IPC分类号： H03M3/00
CPC分类号： H03M7/3006 , H03M7/3042
摘要： Noise that is normally generated during the switching of a noise shaper may be reduced by switching the noise shaper to an inactive or off state after the occurrence of one or more predetermined criteria, for example the detection of a predetermined number of data values below a threshold value or equal to a certain value, or of a predetermined number of data values within a threshold region about a value that is constant with respect to the data values.
摘要翻译：在噪声整形器的切换期间通常产生的噪声可以通过在发生一个或多个预定标准之后将噪声整形器切换到无效或断开状态来减少，例如，检测到低于阈值的预定数量的数据值值或等于某个值，或者阈值区域内的预定数量的数据值关于相对于数据值是恒定的值。

3. 发明授权

US07397873B2 Adaptive signal weighting system 有权
标题翻译：自适应信号加权系统
公开(公告)号：US07397873B2
公开(公告)日：2008-07-08
申请号：US11398431
申请日：2006-04-05
申请人： Matthias Vierthaler , Carsten Noeske
发明人： Matthias Vierthaler , Carsten Noeske
IPC分类号： H04L27/08
CPC分类号： H03G9/14 , H03G9/005 , H04B1/64
摘要： A system for decoding an electrical input signal includes a filter that impresses a variable gain on a portion of the input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.
摘要翻译：用于解码电输入信号的系统包括滤波器，其对输入信号的一部分施加可变增益以去加强输入信号的频谱区域。可变增益被设置为可变增益控制信号的函数。频率检测器根据频率值产生可变增益控制信号，其中输入信号的能量的大约一半低于频率值。

4. 发明申请

US20060181640A1 Adaptive signal weighting system 有权
公开(公告)号：US20060181640A1
公开(公告)日：2006-08-17
申请号：US11398431
申请日：2006-04-05
申请人： Matthias Vierthaler , Carsten Noeske
发明人： Matthias Vierthaler , Carsten Noeske
IPC分类号： H04N11/02
CPC分类号： H03G9/14 , H03G9/005 , H04B1/64
摘要： A system for decoding an electrical input signal includes a filter that impresses a variable gain on a portion of the input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.

5. 发明授权

US07292655B2 Apparatus and method and decoding biphase signals 失效
标题翻译：装置和方法和解码双相信号
公开(公告)号：US07292655B2
公开(公告)日：2007-11-06
申请号：US11441943
申请日：2006-05-26
申请人： Carsten Noeske , Matthias Vierthaler , Thomas Hilpert
发明人： Carsten Noeske , Matthias Vierthaler , Thomas Hilpert
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H04L25/491 , H04L25/06
摘要： A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.
摘要翻译：解码双相信号的技术包括对双相信号进行采样以获得相位采样值并对双相信号进行采样以获得幅度采样值。从相位采样值导出第一数字信号，并且从第一数字信号形成关联位组合。确定比特组合是否是错误比特组合，并且执行概率检查以获得决定错误比特组合的哪些部分为真并且是假的概率值。从所获得的概率值产生校正的比特组合，并且生成其数据状态由有效比特组合形成并且在存在错误比特组合的情况下来自校正比特组合的第二数字信号。

6. 发明申请

US20100235589A1 MEMORY ACCESS CONTROL IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统中的存储器访问控制
公开(公告)号：US20100235589A1
公开(公告)日：2010-09-16
申请号：US12749011
申请日：2010-03-29
申请人： Matthias Vierthaler , Carsten Noeske
发明人： Matthias Vierthaler , Carsten Noeske
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F9/321 , G06F9/3824 , G06F9/526
摘要： Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t≡[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.
摘要翻译：一次一个地向第一处理器和第二处理器中的一个授予执行第一处理器程序的第一处理器和执行第二处理器程序的第二处理器对存储器区域的访问。由第一处理器和第二处理器对第一处理器和第二处理器之间的存储区进行循环唯一地分配（例如，t≡[（ad mod m）= o]）。

7. 发明授权

US07689779B2 Memory access control in a multiprocessor system 失效
标题翻译：多处理器系统中的内存访问控制
公开(公告)号：US07689779B2
公开(公告)日：2010-03-30
申请号：US11503673
申请日：2006-08-14
申请人： Matthias Vierthaler , Carsten Noeske
发明人： Matthias Vierthaler , Carsten Noeske
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F9/321 , G06F9/3824 , G06F9/526
摘要： Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t≡[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.
摘要翻译：一次一个地向第一处理器和第二处理器中的一个授予执行第一处理器程序的第一处理器和执行第二处理器程序的第二处理器对存储器区域的访问。由第一处理器和第二处理器对第一处理器和第二处理器之间的存储区进行循环唯一地分配（例如，t≡[（ad mod m）= o]）。

8. 发明授权

US07046750B1 Adaptive signal weighting system 失效
标题翻译：自适应信号加权系统
公开(公告)号：US07046750B1
公开(公告)日：2006-05-16
申请号：US09897722
申请日：2001-07-02
申请人： Matthias Vierthaler , Carsten Noeske
发明人： Matthias Vierthaler , Carsten Noeske
IPC分类号： H04L27/08
CPC分类号： H03G9/14 , H03G9/005 , H04B1/64
摘要： A system for decoding an electrical input signal includes a filter that impresses a variable gain on the portion of input signal to deemphasize a spectral region of the input signal. The variable gain is set as a function of a variable gain control signal. A frequency detector generates the variable gain control signal in accordance with a frequency value wherein approximately one-half of the energy of the input signal is below the frequency value.
摘要翻译：用于解码电输入信号的系统包括滤波器，其对输入信号的一部分施加可变增益以去加强输入信号的频谱区域。可变增益被设置为可变增益控制信号的函数。频率检测器根据频率值产生可变增益控制信号，其中输入信号的能量的大约一半低于频率值。

9. 发明授权

US06281813B1 Circuit for decoding an analog audio signal 有权
标题翻译：用于解码模拟音频信号的电路
公开(公告)号：US06281813B1
公开(公告)日：2001-08-28
申请号：US09349594
申请日：1999-07-09
申请人： Matthias Vierthaler , Martin Winterer , Stefan Mueller , Thomas Hilpert , Carsten Noeske
发明人： Matthias Vierthaler , Martin Winterer , Stefan Mueller , Thomas Hilpert , Carsten Noeske
IPC分类号： H04N560
CPC分类号： H04N5/607 , H04N5/602 , H04N21/42607 , H04N21/8106
摘要： An integrated circuit for decoding an analog audio signal includes a tuner that receives the analog audio signal and provides a sound intercarrier frequency signal. A digital demodulator receives and digitizes the sound intercarrier frequency signal to provide a digitized sound intercarrier frequency signal, and digitally demodulates the digitized sound intercarrier frequency signal to provide a digitized multichannel television sound (MTS) demodulated signal. A digital broadcast television system committee (BTSC) compatible decoder receives and decodes the digitized multichannel television sound (MTS) demodulated signal, and provides a summed (L+R) audio output signal and a difference (L−R) audio output signal.
摘要翻译：用于解码模拟音频信号的集成电路包括接收模拟音频信号并提供声音载波间频率信号的调谐器。数字解调器接收和数字化声音载波间频率信号，以提供数字化的声音载波间频率信号，并且数字解调数字化的载波间频率信号以提供数字化的多声道电视声音（MTS）解调信号。数字广播电视系统委员会（BTSC）兼容解码器接收并解码数字化的多声道电视声音（MTS）解调信号，并提供加和（L + R）音频输出信号和差分（L-R）音频输出信号。

10. 发明申请

US20070118727A1 Processor for processing data of different data types 有权
标题翻译：用于处理不同数据类型的数据的处理器
公开(公告)号：US20070118727A1
公开(公告)日：2007-05-24
申请号：US11515353
申请日：2006-09-01
申请人： Carsten Noeske , Matthias Vierthaler
发明人： Carsten Noeske , Matthias Vierthaler
IPC分类号： G06F9/44
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30192 , G06F9/34 , G06F9/355
摘要： A processor architecture, for example, a SIMD processor architecture, includes at least two arithmetic/logic units to implement data processing, a data memory arrangement or a memory device interface to a memory arrangement to store data of different data types, an addressing unit to generate access addresses for the data to be stored in the data memory arrangement, and an address memory arrangement to store access addresses. The access addresses are logically linked to the given data type of the data, and/or a distribution of the data to the arithmetic/logic units is dependent on the access addresses, and/or a storage of the output data as the data is dependent on the access addresses.
摘要翻译：例如，SIMD处理器架构的处理器架构包括用于实现数据处理的至少两个算术/逻辑单元，用于存储不同数据类型的数据的存储器装置的数据存储器布置或存储器件接口，寻址单元生成要存储在数据存储装置中的数据的访问地址，以及存储存取地址的地址存储装置。访问地址在逻辑上链接到数据的给定数据类型，和/或数据到算术/逻辑单元的分布取决于访问地址，和/或数据依赖的输出数据的存储在访问地址上。

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