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1. 发明授权

US5717628A Nitride cap formation in a DRAM trench capacitor 失效
公开(公告)号：US5717628A
公开(公告)日：1998-02-10
申请号：US606469
申请日：1996-03-04
申请人： Erwin Hammerl , Herb Lei Ho
发明人： Erwin Hammerl , Herb Lei Ho
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/76 , H01L27/115
CPC分类号： H01L27/10861
摘要： A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench into the oxide collar which surrounds the polysilicon trench fill and isolating it from the single crystal semiconducting substrate material of the DRAM cell to a depth which is at least equal to or larger than the width of the oxide collar. A nitride layer with a thickness equal to or thicker than half of the width of the oxide collar is then deposited on the top surface of the freshly excavated oxide collar such that the aforementioned trench is completely filled with this nitride layer, and the entire surfaces of the substrate and polysilicon trench fill are completely covered. The newly formed nitride layer is then selectively overetched in order to completely remove it from the substrate and polysilicon trench fill surfaces, while still maintaining a sufficient thickness of this layer disposed on the oxide collar sufficient to prevent oxygen diffusion into the oxide collar. Alternatively, the nitride layer may be deposited as a thin layer sandwiched between the original oxide collar and an additional thermally deposited oxide layer.

2. 发明授权

US5937292A Nitride cap formation in a DRAM trench capacitor 失效
标题翻译： DRAM沟槽电容器中的氮化物盖形成
公开(公告)号：US5937292A
公开(公告)日：1999-08-10
申请号：US730839
申请日：1996-10-17
申请人： Erwin Hammerl , Herb Lei Ho
发明人： Erwin Hammerl , Herb Lei Ho
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench into the oxide collar which surrounds the polysilicon trench fill and isolating it from the single crystal semiconducting substrate material of the DRAM cell to a depth which is at least equal to or larger than the width of the oxide collar. A nitride layer with a thickness equal to or thicker than half of the width of the oxide collar is then deposited on the top surface of the freshly excavated oxide collar such that the aforementioned trench is completely filled with this nitride layer, and the entire surfaces of the substrate and polysilicon trench fill are completely covered. The newly formed nitride layer is then selectively overetched in order to completely remove it from the substrate and polysilicon trench fill surfaces, while still maintaining a sufficient thickness of this layer disposed on the oxide collar sufficient to prevent oxygen diffusion into the oxide collar. Alternatively, the nitride layer may be deposited as a thin layer sandwiched between the original oxide collar and an additional thermally deposited oxide layer.
摘要翻译：一种用于在DRAM单元中的沟槽电容器的氧化物环上形成不透氧屏障的方法。该方法包括将浅沟槽蚀刻到环绕多晶硅沟槽填充物的氧化物环中，并将其从DRAM单元的单晶半导体衬底材料隔离到至少等于或大于氧化物环的宽度的深度。然后将厚度等于或大于氧化物环的宽度的一半的氮化物层沉积在新挖出的氧化物环的顶表面上，使得上述沟槽完全填充有该氮化物层，并且整个表面衬底和多晶硅沟槽填充被完全覆盖。然后，新形成的氮化物层被选择性地过蚀刻，以便将其从衬底和多晶硅沟槽填充表面完全去除，同时仍保持设置在氧化物环上的该层的足够厚度足以防止氧气扩散进入氧化物环。或者，可以将氮化物层沉积成夹在原始氧化物环和附加的热沉积氧化物层之间的薄层。

3. 发明授权

US5899724A Method for fabricating a titanium resistor 失效
标题翻译：制造钛电阻的方法
公开(公告)号：US5899724A
公开(公告)日：1999-05-04
申请号：US647392
申请日：1996-05-09
申请人： David Mark Dobuzinsky , Stephen Gerard Fugardi , Erwin Hammerl , Herbert Lei Ho , Samuel C. Ramac , Alvin Wayne Strong
发明人： David Mark Dobuzinsky , Stephen Gerard Fugardi , Erwin Hammerl , Herbert Lei Ho , Samuel C. Ramac , Alvin Wayne Strong
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/20
CPC分类号： H01L28/24
摘要： According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.
摘要翻译：根据本发明的优选实施例，提供一种改进的电阻器和制造方法。将电阻元件制造成集成电路半导体器件的方法包括以下步骤：沉积诸如氮化硅的介电膜; 在电介质膜上沉积钛膜; 并对钛和介电膜进行退火。这导致钛扩散到电介质膜中。这产生具有相对较高电阻率的电阻元件。优选的实施方式具有易于集成到常规集成电路制造技术中的优点。

4. 发明授权

US6153474A Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate 失效
标题翻译：在延伸到半导体衬底的沟槽的垂直延伸的侧壁的一部分上可控地形成LOCOS氧化物层的方法
公开(公告)号：US6153474A
公开(公告)日：2000-11-28
申请号：US108619
申请日：1998-07-01
申请人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
发明人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.
摘要翻译：本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。

5. 发明授权

US5792685A Three-dimensional device layout having a trench capacitor 失效
标题翻译：具有沟槽电容器的三维器件布局
公开(公告)号：US5792685A
公开(公告)日：1998-08-11
申请号：US667541
申请日：1996-06-21
申请人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
发明人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
摘要翻译：公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。

6. 发明授权

US5656535A Storage node process for deep trench-based DRAM 失效
标题翻译：深沟槽DRAM的存储节点处理
公开(公告)号：US5656535A
公开(公告)日：1997-08-12
申请号：US610912
申请日：1996-03-04
申请人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
发明人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
摘要翻译：一种在半导体衬底上制造用于深沟槽DRAM的存储节点的简化方法。该方法包括在衬底的表面中蚀刻沟槽，然后在沟槽的侧壁上形成介电材料层，其顶部部分随后从侧壁去除。接下来，在侧壁的暴露部分上生长一层氧化物。然后从侧壁去除该层氧化物的一部分，以便将氧化层定向到距衬底表面预定的距离。最后，沟槽填充有半导体材料。

7. 发明授权

US5643823A Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures 失效
标题翻译：薄晶体Si3N4衬垫在浅沟槽隔离（STI）结构中的应用
公开(公告)号：US5643823A
公开(公告)日：1997-07-01
申请号：US531844
申请日：1995-09-21
申请人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , J. Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
发明人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , J. Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/318 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3105 , H01L21/32 , H01L21/76224 , Y10S148/05
摘要： Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.
摘要翻译：硅集成电路在浅沟槽隔离（STI）结构中使用氮化硅（Si 3 N 4）的结晶层作为O 2阻挡膜。与沉积的非晶Si3N4相比，晶体Si3N4降低了电子阱的密度。此外，可以沉积更大范围的低压化学气相沉积（LPCVD）Si 3 N 4膜，为厚度可控性提供更大的处理窗口。在720℃至780℃的温度下沉积LPCVD-Si 3 N 4膜。沉积膜处于非晶状态。随后，在1050℃至1100℃下进行纯氮或氨的高温快速热退火60秒。

8. 发明授权

US6140208A Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications 有权
标题翻译：浅沟槽隔离（STI），双层氧化物氮化物用于VLSI应用
公开(公告)号：US6140208A
公开(公告)日：2000-10-31
申请号：US245958
申请日：1999-02-05
申请人： Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
发明人： Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.
摘要翻译：公开了浅沟槽隔离通孔的寄生泄漏的减少，其中通过在沉积氮化硅衬垫之前沉积绝缘氧化物层来增加氮化硅衬垫和有源硅侧壁之间的距离。优选地，绝缘氧化物层包括原硅酸四乙酯。该方法包括将一个或多个浅沟槽隔离件蚀刻成半导体晶片; 将绝缘氧化物层沉积到沟槽中; 在沟槽中生长热氧化物; 以及在沟槽中沉积氮化硅衬垫。热氧化物可以在沉积绝缘氧化物层之前或之后生长。

9. 发明授权

US5827765A Buried-strap formation in a dram trench capacitor 失效
标题翻译：埋地式电容器中的埋地带形成
公开(公告)号：US5827765A
公开(公告)日：1998-10-27
申请号：US605622
申请日：1996-02-22
申请人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
发明人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
摘要翻译：一种用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法。电连接是通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散形成的，该单晶通过从沟槽侧壁外延（epi）生长的单晶半导体材料。该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

10. 发明授权

US5543348A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5543348A
公开(公告)日：1996-08-06
申请号：US412442
申请日：1995-03-29
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.
摘要翻译：提供一种形成耦合电容器和晶体管的方法。在半导体衬底中形成沟槽，然后通过用杂质掺杂的第一导电材料填充沟槽来形成杂质掺杂的第一导电区域。杂质掺杂的第一导电区域被回蚀刻到沟槽内的第一水平。然后在通过杂质掺杂的第一导电区域的蚀刻开口的沟槽部分的侧壁上形成绝缘层，并且通过用第二导电材料填充沟槽的其余部分形成第二导电区域。将绝缘层和第二导电区域回蚀刻到沟槽内的第二层，并且在通过绝缘层和第二导电区域的蚀刻打开的沟槽部分中形成非晶硅层。未掺杂的非晶硅层在沟槽内回蚀刻到第三级。然后将未掺杂的非晶硅层重结晶。杂质通过再结晶硅层从杂质掺杂的第一导电区向外延伸到半导体衬底。晶体管的源极/漏极区域形成为与沟槽和半导体衬底的表面的交点相邻。超扩散杂质和再结晶硅层构成用于将沟槽中的第一和第二导电层电连接到源极/漏极区域的掩埋带。

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