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1. 发明授权

US08245014B2 Thread interleaving in a multithreaded embedded processor 有权
标题翻译：多线程嵌入式处理器中的线程交织
公开(公告)号：US08245014B2
公开(公告)日：2012-08-14
申请号：US12102417
申请日：2008-04-14
申请人： Donald E Steiss , Earl T Cohen , John J Williams
发明人： Donald E Steiss , Earl T Cohen , John J Williams
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802
摘要： The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls.
摘要翻译：本发明提供了一种诸如网络处理器的网络多线程处理器，其包括线程交织器，其执行细粒度线程决定以避免指令执行资源的不充分利用，尽管具有大的通信延迟。在上部流水线中，指令单元响应于每个线程上的指令队列深度来确定指令获取序列。在较低流水线中，线程交织器响应于包括线程等待时间条件的线程状况来确定线程交织序列。线程交织器使用两级循环仲裁来选择线程。线程延迟信号响应于线程延迟（如线程停止，高速缓存未命中和互锁）而有效。在随后的一个或多个时钟周期中，线程不符合仲裁规则。在一个实施例中，其他线程条件影响选择决策，例如本地优先级，全局档位和延迟档。

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