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1. 发明授权

US07979699B2 Processing capacity on demand 有权
标题翻译：按需处理能力
公开(公告)号：US07979699B2
公开(公告)日：2011-07-12
申请号：US10848387
申请日：2004-05-19
申请人： Deep K. Buch , Shivnandan Kaushik
发明人： Deep K. Buch , Shivnandan Kaushik
IPC分类号： H04L29/06
CPC分类号： G06F9/50 , G06F9/5027 , G06F2209/509
摘要： Embodiments of the present invention relate to a system and method for providing processing capacity on demand. According to the embodiments, a processor package has a plurality of processing elements. One or more of the processing elements may be made active in response to increased demand for processing capacity based on modifiable authorization information.
摘要翻译：本发明的实施例涉及一种按需提供处理能力的系统和方法。根据实施例，处理器封装具有多个处理元件。响应于基于可修改的授权信息对处理能力的增加的需求，一个或多个处理元件可以被激活。

2. 发明授权

US07159220B2 Flexible acceleration of java thread synchronization on multiprocessor computers 失效
标题翻译：在多处理器计算机上灵活加速java线程同步
公开(公告)号：US07159220B2
公开(公告)日：2007-01-02
申请号：US09968347
申请日：2001-09-28
申请人： Deep K. Buch
发明人： Deep K. Buch
IPC分类号： G06F9/50
CPC分类号： G06F9/52
摘要： A method and machine-readable medium measure requests by threads requesting a lock to differentiate “hot” and “cold” locks in accordance with the level of contention for the locks. A hardware accelerator manages access to hot locks to improve performance.
摘要翻译：方法和机器可读介质根据锁的争用程度来测量请求锁的线程的请求以区分“热”和“冷”锁。硬件加速器管理访问热锁以提高性能。

3. 发明授权

US06772241B1 Selective interrupt delivery to multiple processors having independent operating systems 有权
标题翻译：选择性中断传递到具有独立操作系统的多个处理器
公开(公告)号：US06772241B1
公开(公告)日：2004-08-03
申请号：US09676463
申请日：2000-09-29
申请人： Varghese George , Edward Gamsaragan , Vladimir M. Pentkovski , Deep K. Buch , Paul Zagacki
发明人： Varghese George , Edward Gamsaragan , Vladimir M. Pentkovski , Deep K. Buch , Paul Zagacki
IPC分类号： G06F500
CPC分类号： G06F9/4812 , G06F13/24 , Y02D10/14 , Y02D10/24
摘要： A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.
摘要翻译：描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。中断由计算机系统中的各种平台设备生成。根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。

4. 发明授权

US07114011B2 Multiprocessor-scalable streaming data server arrangement 有权
公开(公告)号：US07114011B2
公开(公告)日：2006-09-26
申请号：US09941702
申请日：2001-08-30
申请人： Deep K. Buch , Zhenjun Hu , Neil Schaper , David Zhao , Vladimir M. Pentkovski
发明人： Deep K. Buch , Zhenjun Hu , Neil Schaper , David Zhao , Vladimir M. Pentkovski
IPC分类号： G06F15/16
CPC分类号： G06F9/50
摘要： A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0

5. 发明授权

US07080376B2 High performance synchronization of accesses by threads to shared resources 失效
公开(公告)号：US07080376B2
公开(公告)日：2006-07-18
申请号：US09960545
申请日：2001-09-21
申请人： Deep K. Buch
发明人： Deep K. Buch
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/4843
摘要： In one aspect of the invention is a method to synchronize accesses by multiple threads to shared resources. The method entails a first thread entering a processing queue to contend for a lock on a shared resource. If a second thread exists, where the second thread is currently executing code, then the first thread may execute the critical section of code if the second thread is not currently executing the critical section; or if the second thread is currently executing the critical section of code, then the first thread may continue to contend for ownership of the shared resource until the second thread relinquishes ownership of the shared resource, or until a yield count expires.

6. 发明授权

US06901522B2 System and method for reducing power consumption in multiprocessor system 失效
标题翻译：用于降低多处理器系统功耗的系统和方法
公开(公告)号：US06901522B2
公开(公告)日：2005-05-31
申请号：US09876609
申请日：2001-06-07
申请人： Deep K. Buch
发明人： Deep K. Buch
IPC分类号： G06F1/32 , G06F9/46
CPC分类号： G06F1/329 , G06F1/3203 , Y02D10/24
摘要： A method and apparatus for power management is disclosed. The invention reduces power consumption in multiprocessing systems by dynamically adjusting processor power based on system workload. Particularly, the method and apparatus determines the number of required processors based on the number or active threads and sets a processor affinity to run the active threads on the determined number of required processors, thereby allowing the free processors to enter a low-power state.
摘要翻译：公开了一种用于电源管理的方法和装置。本发明通过基于系统工作负载动态调整处理器功率来降低多处理系统的功耗。特别地，该方法和装置基于数量或活动线程来确定所需处理器的数量，并且设置处理器亲和度以在确定数量的所需处理器上运行活动线程，从而允许空闲处理器进入低功率状态。

7. 发明申请

US20160364308A1 PROVIDING AUTONOMOUS SELF-TESTING OF A PROCESSOR 有权
标题翻译：提供处理器的自动自检
公开(公告)号：US20160364308A1
公开(公告)日：2016-12-15
申请号：US14737768
申请日：2015-06-12
申请人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
发明人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
IPC分类号： G06F11/263 , G06F11/22
CPC分类号： G06F11/2635 , G06F11/1417 , G06F11/1433 , G06F11/2242 , G06F11/2268 , G06F11/27
摘要： In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心，功率管理单元，其具有第一测试寄存器，该第一测试寄存器包括第一字段以存储与测试补丁相关联的测试补丁标识符，以及第二字段以存储测试模式指示符以请求核心功能测试，以及微代码存储器，用于存储由所述至少一个核执行的微代码。响应于测试补丁标识符，微代码可以根据从固件接口表获得的地址从非易失性存储器访问固件接口表并获得测试补丁。描述和要求保护其他实施例。

8. 发明申请

US20150089280A1 RECOVERY FROM MULTIPLE DATA ERRORS 有权
标题翻译：从多个数据错误中恢复
公开(公告)号：US20150089280A1
公开(公告)日：2015-03-26
申请号：US14038334
申请日：2013-09-26
申请人： Raanan Sade , Ron Gabor , Deep K. Buch , Theodros Yigzaw , Stanislav Shwartsman
发明人： Raanan Sade , Ron Gabor , Deep K. Buch , Theodros Yigzaw , Stanislav Shwartsman
IPC分类号： G06F11/07
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/08
摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
摘要翻译：提供了同时处理多个数据错误的机制。处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

9. 发明授权

US07506339B2 High performance synchronization of accesses by threads to shared resources 有权
标题翻译：线程访问共享资源的高性能同步
公开(公告)号：US07506339B2
公开(公告)日：2009-03-17
申请号：US11437091
申请日：2006-05-19
申请人： Deep K. Buch
发明人： Deep K. Buch
IPC分类号： G06F9/00
CPC分类号： G06F9/526 , G06F9/4843
摘要： In one aspect of the invention is a method to synchronize accesses by multiple threads to shared resources. The method entails a first thread entering a processing queue to contend for a lock on a shared resource. If a second thread exists, where the second thread is currently executing code, then the first thread may execute the critical section of code if the second thread is not currently executing the critical section; or if the second thread is currently executing the critical section of code, then the first thread may continue to contend for ownership of the shared resource until the second thread relinquishes ownership of the shared resource, or until a yield count expires.
摘要翻译：本发明的一个方面是将多个线程的访问同步到共享资源的方法。该方法需要第一个线程进入处理队列以争取共享资源上的锁定。如果第二个线程存在第二个线程正在执行代码的第二个线程，那么如果第二个线程当前没有执行临界部分，则第一个线程可以执行代码的关键部分; 或者如果第二个线程当前正在执行代码的关键部分，那么第一个线程可能会继续争夺共享资源的所有权，直到第二个线程放弃共享资源的所有权，或直到产生计数到期。

10. 发明授权

US06976099B2 Selective interrupt delivery to multiple processors having independent operating systems 失效
标题翻译：选择性中断传递到具有独立操作系统的多个处理器
公开(公告)号：US06976099B2
公开(公告)日：2005-12-13
申请号：US10865220
申请日：2004-06-09
申请人： Varghese George , Edward Gamsaragan , Vladimir M. Pentkovski , Deep K. Buch , Paul Zagacki
发明人： Varghese George , Edward Gamsaragan , Vladimir M. Pentkovski , Deep K. Buch , Paul Zagacki
IPC分类号： G06F9/48 , G06F13/24 , G06F5/00
CPC分类号： G06F9/4812 , G06F13/24 , Y02D10/14 , Y02D10/24
摘要： A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.
摘要翻译：描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。中断由计算机系统中的各种平台设备生成。根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。

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