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1. 发明申请

US20090143884A1 SYSTEMS AND METHODS FOR SAMPLE RATE CONVERSION 有权
标题翻译：用于样本速率转换的系统和方法
公开(公告)号：US20090143884A1
公开(公告)日：2009-06-04
申请号：US12343317
申请日：2008-12-23
申请人： Daniel L.W. Chieng , Jack B. Andersen , Larry E. Hand
发明人： Daniel L.W. Chieng , Jack B. Andersen , Larry E. Hand
IPC分类号： G06F17/00 , H04L7/00
CPC分类号： H03F3/217 , H03F2200/03 , H03H17/0275 , H03H17/0642 , H03H17/0685
摘要： Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.
摘要翻译：提供了用于将具有可变输入采样率的输入数据流转换为输出采样率的系统和方法，哪些系统和方法用于处理数据流。在一个实施例中，系统包括时钟源，被配置为对相应数据流计数周期的计数器和数据处理器。数据处理器被配置为读取由接收到的帧同步信号之间的计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率。

2. 发明申请

US20090027117A1 Low-Noise, Low-Distortion Digital PWM Amplifier 有权
标题翻译：低噪声，低失真数字PWM放大器
公开(公告)号：US20090027117A1
公开(公告)日：2009-01-29
申请号：US11782702
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38
CPC分类号： H03F1/3258 , H03F1/26 , H03F1/3241 , H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译：使用低通滤波技术降低噪声和失真的数字开关放大器性能改进的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。放大器还包括一个低通滤波器，用于滤除工厂输出的音频信号。工厂的滤波输出作为反馈被添加到输入音频信号。该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

3. 发明申请

US20090027118A1 Digital PWM Amplifier Having a Low Delay Corrector 有权
标题翻译：具有低延迟校正器的数字PWM放大器
公开(公告)号：US20090027118A1
公开(公告)日：2009-01-29
申请号：US11782708
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38 , H03G3/10
CPC分类号： H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译：使用低延迟校正器的数字开关放大器性能改进的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。放大器还包括低延迟校正器，其被配置为接收由工厂输出的信号。低延迟校正器的输出作为反馈被添加到输入音频信号。该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

4. 发明申请

US20090302938A1 LOW DELAY CORRECTOR 有权
标题翻译：低延迟校正器
公开(公告)号：US20090302938A1
公开(公告)日：2009-12-10
申请号：US12542634
申请日：2009-08-17
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L.W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38 , H03G3/12
CPC分类号： H03F3/217
摘要： A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.
摘要翻译：低延迟校正器（LDC）单元包括非线性函数发生器和滤波器。非线性函数发生器接收第一信号并根据第一信号和非线性函数发生器的传递函数输出第二信号。滤波器根据由非线性函数发生器输出的第二信号进给。根据提供给LDC单元的输入的输入信号和滤波器的输出，导出由非线性函数发生器接收到的第一信号。根据由非线性函数发生器接收到的第一信号和由非线性函数发生器输出的第二信号，导出LDC单元的输出。

5. 发明申请

US20080278230A1 Systems and Methods for Correcting Errors Resulting from Component Mismatch in a Feedback Path 有权
标题翻译：用于纠正由反馈路径中的组件不匹配引起的错误的系统和方法
公开(公告)号：US20080278230A1
公开(公告)日：2008-11-13
申请号：US11672331
申请日：2007-02-07
申请人： Michael A. Kost , Jack B. Andersen , Daniel L.W. Chieng
发明人： Michael A. Kost , Jack B. Andersen , Daniel L.W. Chieng
IPC分类号： H03F3/38
CPC分类号： H03F3/2173 , H03F1/30 , H03F1/34 , H03F2200/03 , H03F2200/351
摘要： Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.
摘要翻译：用于使数字PWM放大器反馈回路的反馈路径中的组件不匹配导致性能下降最小化的系统和方法。一个实施例包括具有反馈的数字脉宽调制（PWM）放大器。放大子系统接收数字音频信号并产生模拟输出信号。反馈回路基于滤波的模拟输出信号产生反馈信号，并且基于反馈信号修改数字音频信号。反馈回路包括被配置为过滤模拟输出信号的滤波器和被配置为校正由滤波器引入的元件失配误差的校正电路。在一个实施例中，校正电路接收电源电压的测量，将测量的电压乘以增益，并将缩放的测量值加到反馈信号上，以校正组件失配误差。

6. 发明授权

US07970088B2 Systems and methods for sample rate conversion 有权
标题翻译：采样率转换的系统和方法
公开(公告)号：US07970088B2
公开(公告)日：2011-06-28
申请号：US12343317
申请日：2008-12-23
申请人： Daniel L. W. Chieng , Jack B. Andersen , Larry E. Hand
发明人： Daniel L. W. Chieng , Jack B. Andersen , Larry E. Hand
IPC分类号： H04L7/00
CPC分类号： H03F3/217 , H03F2200/03 , H03H17/0275 , H03H17/0642 , H03H17/0685
摘要： Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.
摘要翻译：提供了用于将具有可变输入采样率的输入数据流转换为输出采样率的系统和方法，哪些系统和方法用于处理数据流。在一个实施例中，系统包括时钟源，被配置为对相应数据流计数周期的计数器和数据处理器。数据处理器被配置为读取由接收到的帧同步信号之间的计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率。

7. 发明授权

US07576606B2 Digital PWM amplifier having a low delay corrector 有权
标题翻译：数字PWM放大器具有低延迟校正器
公开(公告)号：US07576606B2
公开(公告)日：2009-08-18
申请号：US11782708
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译：使用低延迟校正器的数字开关放大器性能改进的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。放大器还包括低延迟校正器，其被配置为接收由工厂输出的信号。低延迟校正器的输出作为反馈被添加到输入音频信号。该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

8. 发明授权

US07929718B1 Systems and methods for switching and mixing signals in a multi-channel amplifier 有权
标题翻译：用于在多通道放大器中切换和混合信号的系统和方法
公开(公告)号：US07929718B1
公开(公告)日：2011-04-19
申请号：US10843852
申请日：2004-05-12
申请人： Douglas D. Gephardt , Jack B. Andersen , Larry E. Hand
发明人： Douglas D. Gephardt , Jack B. Andersen , Larry E. Hand
IPC分类号： H03F99/00 , H02B1/00 , H04R29/00 , G06F17/00
CPC分类号： H03F3/68 , H03F3/217
摘要： Systems and methods for scaling the number of output channels that can be provided in an audio amplification system. In one embodiment, a digital pulse width modulation (PWM) amplification system includes multiple four-channel PWM controller chips that are interconnected to enable synchronization and transfer of digital audio data from one chip to another. Input audio signals received by each of the channels are processed by sample rate converters to generate internal audio signals that have a predetermined sample rate and format. Each of the channels is synchronized so that the internal audio signal of each channel can be processed and output by any of the other channels. The PWM controller chips are connected by a high-speed interconnect that enables the transfer of data between them. Each input audio signal can be mapped to any of the outputs and can be mixed with other input signals.
摘要翻译：用于缩放可在音频放大系统中提供的输出通道数量的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大系统包括互连的多个四通道PWM控制器芯片，以实现数字音频数据从一个芯片到另一个芯片的同步和传输。由每个通道接收的输入音频信号由采样率转换器处理以产生具有预定采样率和格式的内部音频信号。每个通道被同步，使得每个通道的内部音频信号可以被任何其他通道处理和输出。 PWM控制器芯片通过高速互连连接，可以在它们之间传输数据。每个输入音频信号可以映射到任何一个输出，并且可以与其他输入信号混合。

9. 发明授权

US07812666B2 Low delay corrector 有权
标题翻译：低延迟校正器
公开(公告)号：US07812666B2
公开(公告)日：2010-10-12
申请号：US12542634
申请日：2009-08-17
申请人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
发明人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/68
CPC分类号： H03F3/217
摘要： A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.
摘要翻译：低延迟校正器（LDC）单元包括非线性函数发生器和滤波器。非线性函数发生器接收第一信号并根据第一信号和非线性函数发生器的传递函数输出第二信号。滤波器根据由非线性函数发生器输出的第二信号进给。根据提供给LDC单元的输入的输入信号和滤波器的输出，导出由非线性函数发生器接收到的第一信号。根据由非线性函数发生器接收到的第一信号和由非线性函数发生器输出的第二信号，导出LDC单元的输出。

10. 发明授权

US07728658B2 Low-noise, low-distortion digital PWM amplifier 有权
标题翻译：低噪声，低失真的数字PWM放大器
公开(公告)号：US07728658B2
公开(公告)日：2010-06-01
申请号：US11782702
申请日：2007-07-25
申请人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38 , H03F1/30
CPC分类号： H03F1/3258 , H03F1/26 , H03F1/3241 , H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译：使用低通滤波技术降低噪声和失真的数字开关放大器性能改进的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。放大器还包括一个低通滤波器，用于滤除工厂输出的音频信号。工厂的滤波输出作为反馈被添加到输入音频信号。该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

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