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    • 1. 发明授权
    • Power supply system with function of short circuit detection
    • 具有短路检测功能的电源系统
    • US07656116B2
    • 2010-02-02
    • US12181733
    • 2008-07-29
    • Takehiro YanoTetsu NaganoDaisuke Fukuda
    • Takehiro YanoTetsu NaganoDaisuke Fukuda
    • H02P27/04
    • H02H7/0838
    • There are provided upper and lower switching elements 1U to 1W and 2U to 2W for energizing motor drive windings 4U to 4W, a control circuit 20 that starts outputting a control signal for energization based on an energization instruction, pre-drive circuits 8U to 8W and 9U to 9W for controlling ON/OFF of the upper and lower switching elements based on the control signal, and short circuit detection circuits 10U to 10W for detecting short circuits in a node 14 between the upper and lower switching elements to higher-potential and lower-potential power sources based on the control signal and a voltage of the node. The short circuit detection circuits are controlled to detect a short circuit in the node to the lower-potential power source with all the upper switching elements turned ON and all the lower switching elements turned OFF and to detect a short circuit in the node to the higher-potential power source with all the upper switching elements turned OFF and all the lower switching elements turned ON, in a state where the motor drive windings are not energized. It is possible to prevent a situation in which a short circuit cannot be detected depending on a resistance component of a drive target.
    • 设置用于对电动机驱动绕组4U〜4W供电的上下开关元件1U〜1W和2U〜2W,基于通电指令开始输出用于通电的控制信号的控制电路20,预驱动电路8U〜8W, 9U至9W,用于根据控制信号控制上下开关元件的ON / OFF;以及短路检测电路10U至10W,用于检测上下开关元件之间的节点14中的短路到较高电位和较低电位 基于控制信号的电源和节点的电压。 控制短路检测电路,以便在所有上部开关元件导通并且所有下部开关元件断开并且将节点中的短路检测到较高的电平时检测节点中的低电位电源的短路 在电动机驱动绕组未被通电的状态下,所有上部开关元件关闭并且所有下部开关元件导通的电位电源。 可以防止根据驱动目标的电阻分量而不能检测短路的情况。
    • 2. 发明申请
    • OUTPUT BUFFER CIRCUIT AND OUTPUT BUFFER SYSTEM
    • 输出缓冲电路和输出缓冲器系统
    • US20110002073A1
    • 2011-01-06
    • US12885127
    • 2010-09-17
    • Daisuke FUKUDATetsu NaganoTakehiro Yano
    • Daisuke FUKUDATetsu NaganoTakehiro Yano
    • H02H3/00
    • H03F1/523H03F3/2173H03K17/0822
    • An output buffer circuit of the present invention includes: a first output circuit having a first upper switching element and a first lower switching element, the first upper switching element having main terminals, one of the main terminals being maintained at a first voltage, the first lower switching element having main terminals, one of the main terminals being connected to the other main terminal of the upper switching element, the other main terminal of the first lower switching element being maintained at a second voltage, a portion where the other main terminal of the first upper switching element and one of the main terminals of the first lower switching element are connected to each other constituting an output portion for output to outside; a second output circuit having an output terminal connected to the output portion of the first output circuit; and a short-circuit detecting circuit configured to detect a short circuit of the output portion of the first output circuit. The output buffer circuit of the present invention is configured such that: when starting up the output buffer circuit, the second output circuit and the short-circuit detecting circuit are activated before activating the first output circuit; when the short circuit of the output portion is not detected, the first output circuit is activated; and when the short circuit of the output portion is detected, the first output circuit is not activated.
    • 本发明的输出缓冲电路包括:具有第一上开关元件和第一下开关元件的第一输出电路,所述第一上开关元件具有主端子,所述主端子中的一个保持在第一电压,所述第一上开关元件 下开关元件具有主端子,一个主端子连接到上开关元件的另一主端子,第一下开关元件的另一主端子保持在第二电压,另一主端子 第一上开关元件和第一下开关元件的主端子中的一个彼此连接构成输出部分以输出到外部; 第二输出电路,其输出端连接到第一输出电路的输出部分; 以及短路检测电路,被配置为检测第一输出电路的输出部分的短路。 本发明的输出缓冲电路被配置为:在启动输出缓冲电路时,第二输出电路和短路检测电路在激活第一输出电路之前被激活; 当未检测到输出部分的短路时,第一输出电路被激活; 并且当检测到输出部分的短路时,第一输出电路不被激活。
    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07646246B2
    • 2010-01-12
    • US12056860
    • 2008-03-27
    • Shinichiro KataokaTakehiro Yano
    • Shinichiro KataokaTakehiro Yano
    • H03F1/14
    • H03F1/14H03F3/45183H03F2200/153H03F2203/45466H03F2203/45512H03F2203/45641H03F2203/45654H03F2203/45674
    • A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g., as a phase compensation circuit element of an operational amplifier, the MOS capacitance is not reduced, no matter the range of the input or output voltage of the operational amplifier, so that the phase margin will not reduced.
    • 半导体器件包括使用具有绝缘膜设置在形成在半导体衬底上的栅电极和扩散层之间的结构的MOS电容器的相位补偿电路6。 相位补偿电路包括第一和第二MOS电容器14,15。第一MOS电容器的栅电极端子等效地连接到作为与栅电极端子相对的端子的第二MOS电容器的扩散层端子。 在第一MOS电容器的扩散层端子和第二MOS电容器的栅电极端子之间连接有通过使电流流过而产生电位差的电位差产生元件16。 当使用具有电压依赖性的MOS电容器时,例如,作为运算放大器的相位补偿电路元件,不考虑运算放大器的输入或输出电压的范围,MOS电容不降低,使得相位 保证金不会减少。
    • 4. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20080238552A1
    • 2008-10-02
    • US12056860
    • 2008-03-27
    • Shinichiro KataokaTakehiro Yano
    • Shinichiro KataokaTakehiro Yano
    • H03F1/14
    • H03F1/14H03F3/45183H03F2200/153H03F2203/45466H03F2203/45512H03F2203/45641H03F2203/45654H03F2203/45674
    • A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g., as a phase compensation circuit element of an operational amplifier, the MOS capacitance is not reduced, no matter the range of the input or output voltage of the operational amplifier, so that the phase margin will not reduced.
    • 半导体器件包括使用具有绝缘膜设置在形成在半导体衬底上的栅电极和扩散层之间的结构的MOS电容器的相位补偿电路6。 相位补偿电路包括第一和第二MOS电容器14,15。 第一MOS电容器的栅极端子等效地连接到与栅电极端子相对的端子的第二MOS电容器的扩散层端子。 在第一MOS电容器的扩散层端子和第二MOS电容器的栅电极端子之间连接有通过使电流流过而产生电位差的电位差产生元件16。 当使用具有电压依赖性的MOS电容器时,例如,作为运算放大器的相位补偿电路元件,不考虑运算放大器的输入或输出电压的范围,MOS电容不降低,使得相位 保证金不会减少。
    • 5. 发明授权
    • Stepping motor drive device
    • 步进电机驱动装置
    • US08508177B2
    • 2013-08-13
    • US12984415
    • 2011-01-04
    • Takehiro Yano
    • Takehiro Yano
    • H02P8/00H02P8/14
    • H02P8/14H02P8/36
    • A stepping motor drive device includes: a first pulse generation circuit that generates pulses at rising or falling edges of a first clock signal; a second pulse generation circuit that generates pulses at rising and falling edges of a second clock signal; a first mask circuit that outputs or masks the output of the first pulse generation circuit depending on whether the second clock signal is normal; a second mask circuit that outputs or masks the output of the second pulse generation circuit depending on whether the first clock signal is normal; a logic circuit that logically combines the outputs of the mask circuits; a step position control circuit that determines the step position of a motor according to the output of the logic circuit; and a motor drive section that supplies a current to the motor according to the output of the step position control circuit.
    • 步进电机驱动装置包括:第一脉冲发生电路,其在第一时钟信号的上升沿或下降沿产生脉冲; 第二脉冲发生电路,在第二时钟信号的上升沿和下降沿产生脉冲; 第一掩模电路,其根据所述第二时钟信号是否正常而输出或掩蔽所述第一脉冲发生电路的输出; 第二掩模电路,其根据第一时钟信号是否正常而输出或屏蔽第二脉冲发生电路的输出; 逻辑电路,逻辑组合掩模电路的输出; 步进位置控制电路,根据逻辑电路的输出确定电机的步进位置; 以及电动机驱动部,其根据步进位置控制电路的输出向电动机供给电流。
    • 6. 发明授权
    • Semiconductor device and method for inspecting the same
    • 半导体装置及其检查方法
    • US07948728B2
    • 2011-05-24
    • US12054968
    • 2008-03-25
    • Shinichiro KataokaTakehiro Yano
    • Shinichiro KataokaTakehiro Yano
    • H02H3/24H02H9/00H02H3/00
    • G01R31/3012
    • A semiconductor device of the present invention includes: a power input terminal; an internal power supply circuit that converts a voltage supplied from the outside to the power input terminal into a predetermined voltage; an analog circuit connected to an output side of the internal power supply circuit; an internal power output terminal connected to the output side of the internal power supply circuit; a logic circuit power input terminal; a logic circuit connected to the logic circuit power input terminal; and interterminal wiring connecting the internal power output terminal to the logic circuit power input terminal. The internal power supply circuit has a configuration of supplying power to the analog circuit and the logic circuit, and in a package assembly (finished product), a resting current in the logic circuit can be inspected without being influence by a consumption current in the analog circuit.
    • 本发明的半导体器件包括:电源输入端子; 内部电源电路,其将从外部供给到电力输入端子的电压转换为预定电压; 连接到所述内部电源电路的输出侧的模拟电路; 内部电力输出端子,连接到内部电源电路的输出侧; 逻辑电路电源输入端; 连接到逻辑电路电源输入端的逻辑电路; 以及将内部功率输出端子连接到逻辑电路电源输入端子的互连线。 内部电源电路具有向模拟电路和逻辑电路供电的配置,并且在封装组件(成品)中,可以检查逻辑电路中的静止电流,而不受模拟量中的消耗电流的影响 电路。