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1. 发明授权

US09008602B2 Radio frequency switch for diversity receiver 有权
标题翻译：用于分集接收机的射频开关
公开(公告)号：US09008602B2
公开(公告)日：2015-04-14
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H04B1/06 , H04B1/44 , H03C7/02 , H01Q11/12 , H04M1/00 , H04B1/16 , H04B1/00 , H04B7/08
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
摘要翻译：分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。第一级开关可以被配置为处理与第二级开关不同的功率量。分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。第二级开关可以被配置为处理比每个第一级开关更多的功率。

2. 发明授权

US08907450B2 Metal-semiconductor wafer bonding for high-Q devices 有权
标题翻译：用于高Q器件的金属半导体晶片接合
公开(公告)号：US08907450B2
公开(公告)日：2014-12-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
IPC分类号： H01L29/92 , H01L21/02 , H01G4/12 , H01G4/33 , H01L49/02
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
摘要翻译：提供了用于高Q装置的金属半导体晶片接合的方法和装置。示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。重掺杂的非本征半导体层接触电介质层。电介质和非本征半导体层夹在第一和第二板之间。在第一板和电介质层之间形成金属间层。金属间化合物层被热压接合到第一板和电介质层。电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

3. 发明申请

US20130295866A1 RADIO FREQUENCY SWITCH FOR DIVERSITY RECEIVER 有权
公开(公告)号：US20130295866A1
公开(公告)日：2013-11-07
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H04B1/16
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

4. 发明申请

US20130222060A1 MUTUALLY COUPLED MATCHING NETWORK 审中-公开
标题翻译： MUTUALLY耦合匹配网络
公开(公告)号：US20130222060A1
公开(公告)日：2013-08-29
申请号：US13406431
申请日：2012-02-27
申请人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
发明人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
IPC分类号： H03H7/38 , H03F1/00
CPC分类号： H03H7/38 , H03H7/09
摘要： An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.
摘要翻译：公开了一种阻抗匹配电路。阻抗匹配电路包括两个或更多个相互耦合的电感器。阻抗匹配电路的总自感小于包括不相互耦合的电感器的对应阻抗匹配电路。两个或更多个相互耦合的电感器可以具有与相应的阻抗匹配电路中的电流比匹配的已知电流比。

5. 发明授权

US09270254B2 Cross-sectional dilation mode resonators and resonator-based ladder filters 有权
标题翻译：横截面扩张模式谐振器和基于谐振器的梯形滤波器
公开(公告)号：US09270254B2
公开(公告)日：2016-02-23
申请号：US13295978
申请日：2011-11-14
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Wesley Nathaniel Allen , Mario Francisco Velez , Jonghae Kim , Sanghoon Joo
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Wesley Nathaniel Allen , Mario Francisco Velez , Jonghae Kim , Sanghoon Joo
IPC分类号： H03H9/15 , H03H9/46 , H03H9/24 , H03H9/54 , H03H9/02
CPC分类号： H03H9/462 , H03H9/02228 , H03H9/2405 , H03H9/2426 , H03H2009/02503 , H03H2009/241
摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.
摘要翻译：公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T）。厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号到一个或多个电极。梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

6. 发明授权

US09083300B2 Electromechanical systems piezoelectric contour mode differential resonators and filters 有权
标题翻译：机电系统压电轮廓模式差动谐振器和滤波器
公开(公告)号：US09083300B2
公开(公告)日：2015-07-14
申请号：US13094707
申请日：2011-04-26
申请人： Chi Shun Lo , Jonghae Kim , Sang-June Park , Sanghoon Joo , Chengjie Zuo , Changhan Yun
发明人： Chi Shun Lo , Jonghae Kim , Sang-June Park , Sanghoon Joo , Chengjie Zuo , Changhan Yun
IPC分类号： H03H9/70 , H03H9/00 , H01P1/213 , H03H9/02 , H03H9/24 , H03H9/56 , G09G3/34 , H03H3/02
CPC分类号： H03H9/0095 , G09G3/3493 , G09G2310/0267 , G09G2310/027 , H01P1/2135 , H03H9/0014 , H03H9/02228 , H03H9/2431 , H03H9/2436 , H03H9/2463 , H03H9/564 , H03H2003/027 , H03H2009/02496 , H03H2009/02527 , H03H2009/241
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a contour mode resonator device includes a first conductive layer with a plurality of first layer electrodes including a first electrode at which a first input signal can be provided and a second electrode at which a first output signal can be provided. A second conductive layer includes a plurality of second layer electrodes including a first electrode proximate the first electrode of the first conductive layer and a second electrode proximate the second electrode of the first conductive layer. A second signal can be provided at the first electrode or the second electrode of the second conductive layer to cooperate with the first input signal or the first output signal to define a differential signal. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer. The piezoelectric layer includes a piezoelectric material. The piezoelectric layer is substantially oriented in a plane and capable of movement in the plane responsive to an electric field between the first electrodes or the second electrodes.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。一方面，轮廓模式谐振器装置包括具有多个第一层电极的第一导电层，所述第一导电层包括能够提供第一输入信号的第一电极和可以提供第一输出信号的第二电极。第二导电层包括多个第二层电极，其包括靠近第一导电层的第一电极的第一电极和靠近第一导电层的第二电极的第二电极。可以在第二导电层的第一电极或第二电极处提供第二信号，以与第一输入信号或第一输出信号配合以限定差分信号。压电层设置在第一导电层和第二导电层之间。压电层包括压电材料。压电层基本上定向在平面中并且能够响应于第一电极或第二电极之间的电场在平面中移动。

7. 发明授权

US08987976B2 Piezoelectric resonator having combined thickness and width vibrational modes 有权
标题翻译：具有组合厚度和宽度振动模式的压电谐振器
公开(公告)号：US08987976B2
公开(公告)日：2015-03-24
申请号：US13241356
申请日：2011-09-23
申请人： Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Changhan Yun , Jonghae Kim
发明人： Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Changhan Yun , Jonghae Kim
IPC分类号： H01L41/047 , H03H9/02 , H03H9/56
CPC分类号： H03H9/02157 , H03H9/02062 , H03H9/56
摘要： A method and apparatus for a piezoelectric resonator having combined thickness and width vibrational modes are disclosed. A piezoelectric resonator may include a piezoelectric substrate and a first electrode coupled to a first surface of the piezoelectric substrate. The piezoelectric resonator may further include a second electrode coupled to a second surface of the piezoelectric substrate, where the first surface and the second surface are substantially parallel and define a thickness dimension of the piezoelectric substrate. Furthermore, the thickness dimension and the width dimension of the piezoelectric substrate are configured to produce a resonance from a coherent combination of a thickness vibrational mode and a width vibrational mode when an excitation signal is applied to the electrodes.
摘要翻译：公开了一种具有组合的厚度和宽度振动模式的压电谐振器的方法和装置。压电谐振器可以包括压电衬底和耦合到压电衬底的第一表面的第一电极。压电谐振器还可以包括耦合到压电基板的第二表面的第二电极，其中第一表面和第二表面基本平行并且限定压电基板的厚度尺寸。此外，压电基板的厚度尺寸和宽度尺寸被构造成当激励信号施加到电极时，从厚度振动模式和宽度振动模式的相干组合产生谐振。

8. 发明授权

US08816567B2 Piezoelectric laterally vibrating resonator structure geometries for spurious frequency suppression 有权
标题翻译：压电横向振动谐振器结构几何形状用于杂散频率抑制
公开(公告)号：US08816567B2
公开(公告)日：2014-08-26
申请号：US13186281
申请日：2011-07-19
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
IPC分类号： H01L41/04 , H03H3/02 , H03H9/02 , H03H9/17
CPC分类号： H03H9/02228 , H03H3/02 , H03H9/02055 , H03H9/173 , H03H2003/021 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a resonator structure includes a first conductive layer of electrodes and a second conductive layer of electrodes. A piezoelectric layer including a piezoelectric material is disposed between the first conductive layer and the second conductive layer. One or more trenches can be formed in the piezoelectric layer on one or both sides in space regions between the electrodes. In some implementations, a process for forming the resonator structure includes removing an exposed portion of the piezoelectric layer to define a trench, for instance, by partial etching or performing an isotropic release etch using a XeF2 gas or SF6 plasma. In some other implementations, a portion of a sacrificial layer is removed to define a trench in the piezoelectric layer.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。一方面，谐振器结构包括电极的第一导电层和电极的第二导电层。包括压电材料的压电层设置在第一导电层和第二导电层之间。一个或多个沟槽可以在电极之间的空间区域的一侧或两侧的压电层中形成。在一些实施方案中，用于形成谐振器结构的工艺包括去除压电层的暴露部分以限定沟槽，例如通过部分蚀刻或使用XeF 2气体或SF 6等离子体进行各向同性释放蚀刻。在一些其他实施方案中，去除牺牲层的一部分以在压电层中限定沟槽。

9. 发明申请

US20130120081A1 COMBINED RESONATORS AND PASSIVE CIRCUIT COMPONENTS FOR FILTER PASSBAND FLATTENING 审中-公开
标题翻译：组合式谐振器和无源电路组件，用于滤波器平滑
公开(公告)号：US20130120081A1
公开(公告)日：2013-05-16
申请号：US13295955
申请日：2011-11-14
申请人： Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Changhan Yun , Jonghae Kim
发明人： Chengjie Zuo , Chi Shun Lo , Sanghoon Joo , Changhan Yun , Jonghae Kim
IPC分类号： H03H9/54 , G06F3/038
CPC分类号： H03H9/542 , H03H9/02228 , H03H9/564
摘要： This disclosure provides implementations of electromechanical systems combined resonator and passive circuit components. In one aspect, passband flattened filter apparatus includes a resonator structure and input and output passband flattening components. The resonator structure has a first input, a second input coupled to a ground terminal, a first output, and a second output coupled to the ground terminal. The input passband flattening component includes a first inductor having an output coupled to the first input of the resonator structure, and a second inductor having an input coupled to the first input of the resonator structure and an output coupled to the ground terminal. The output passband flattening component includes a first inductor having an input coupled to the first output of the resonator structure, and a second inductor having an input coupled to the first output of the resonator structure and an output coupled to the ground terminal.
摘要翻译：本公开提供了机电系统组合谐振器和无源电路部件的实现。一方面，通带扁平滤波器装置包括谐振器结构以及输入和输出通带扁平部件。谐振器结构具有耦合到接地端子的第一输入端，第二输入端，第一输出端和耦合到接地端子的第二输出端。输入通带平坦化部件包括具有耦合到谐振器结构的第一输入的输出的第一电感器和具有耦合到谐振器结构的第一输入的输入端和耦合到接地端子的输出的第二电感器。输出通带平坦化部件包括具有耦合到谐振器结构的第一输出的输入的第一电感器和具有耦合到谐振器结构的第一输出的输入端和耦合到接地端子的输出的第二电感器。

10. 发明申请

US20130120951A1 STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME 有权
标题翻译：具有绝缘层和二次层的堆叠CMOS芯片及其形成方法
公开(公告)号：US20130120951A1
公开(公告)日：2013-05-16
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H05K1/03 , H01L21/60 , H05K7/06 , H01L21/58
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译：芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。还有一种形成芯片组的方法。

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