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1. 发明授权

US06853236B1 Circuit apparatus operable under high voltage 有权
标题翻译：电路设备可在高电压下工作
公开(公告)号：US06853236B1
公开(公告)日：2005-02-08
申请号：US10680241
申请日：2003-10-08
申请人： Chao-Cheng Lee , Ming-Cheng Chiang
发明人： Chao-Cheng Lee , Ming-Cheng Chiang
IPC分类号： H03F1/52 , H03F3/45 , H03F3/72 , H03K17/04 , H03K17/0416 , H03K17/10 , H03K19/0175 , H03K17/687
CPC分类号： H03F3/45183 , H03F1/523 , H03F3/72 , H03K17/04163 , H03K17/102
摘要： An analog circuit apparatus connected to a high voltage source includes a transistor and an interface unit. The transistor has a low operation voltage smaller than the high voltage source and a breakdown voltage. The interface unit is coupled to the transistor in series for preventing the low operation voltage higher than the breakdown voltage.
摘要翻译：连接到高电压源的模拟电路装置包括晶体管和接口单元。晶体管的工作电压低于高电压源和击穿电压。接口单元串联耦合到晶体管，以防止低于击穿电压的低工作电压。

2. 发明授权

US08125811B2 Content-addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08125811B2
公开(公告)日：2012-02-28
申请号：US12561539
申请日：2009-09-17
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G11C15/04
摘要： A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first comparison result; and a first CMOS logic circuit for performing a logic operation on the first comparison result and outputting a first matching result. The second memory unit includes: a second data memory cell for storing a second data bit; a second comparison circuit for comparing a second search bit with the second data bit to determine if there is a match, and outputting a second comparison result; and a second static CMOS logic circuit for performing a logic operation on the first matching result and the second comparison result, and outputting an output matching result.
摘要翻译： CAM包括第一和第二存储器单元。第一存储单元包括：用于存储第一数据位的第一数据存储单元; 第一比较电路，用于将第一搜索位与第一数据位进行比较，以确定是否存在匹配，并输出第一比较结果; 以及第一CMOS逻辑电路，用于对第一比较结果执行逻辑运算并输出第一匹配结果。第二存储器单元包括：用于存储第二数据位的第二数据存储单元; 第二比较电路，用于将第二搜索位与第二数据位进行比较，以确定是否存在匹配，并输出第二比较结果; 以及第二静态CMOS逻辑电路，用于对第一匹配结果和第二比较结果执行逻辑运算，并输出输出匹配结果。

3. 发明授权

US07492225B2 Gain-controlled amplifier 有权
标题翻译：增益控制放大器
公开(公告)号：US07492225B2
公开(公告)日：2009-02-17
申请号：US11781271
申请日：2007-07-22
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F2203/45471 , H03F2203/45496 , H03F2203/45504 , H03F2203/45648 , H03G1/0029 , H03G1/0088
摘要： A gain-controlled amplifier is disclosed including: a set of switches; first and second transistors whose second terminals are coupled to each other via a resistive element; a first current mirror, coupled to a first terminal of the first transistor, for providing a set of first currents; a second current mirror, coupled to a first terminal of the second transistor, for providing a set of second currents; a first resistive network, coupled to the second terminal of the first transistor via a current source, for providing a first output signal; and a second resistive network, coupled to the second terminal of the second transistor via another current source, for providing a second output signal. Both the first and second resistive networks have a plurality of taps, coupling to either a first current or a second current through a switch of the set of switches.
摘要翻译：公开了一种增益控制放大器，包括：一组开关; 第一和第二晶体管，其第二端子经由电阻元件彼此耦合; 第一电流镜，耦合到第一晶体管的第一端，用于提供一组第一电流; 第二电流镜，耦合到所述第二晶体管的第一端，用于提供一组第二电流; 第一电阻网络，经由电流源耦合到第一晶体管的第二端子，用于提供第一输出信号; 以及第二电阻网络，其经由另一个电流源耦合到第二晶体管的第二端子，用于提供第二输出信号。第一和第二电阻网络都具有多个抽头，其耦合到通过该组开关的开关的第一电流或第二电流。

4. 发明授权

US07828704B1 Combination limb and abdominal exerciser 有权
标题翻译：组合肢体和腹部锻炼者
公开(公告)号：US07828704B1
公开(公告)日：2010-11-09
申请号：US12536867
申请日：2009-08-06
申请人： Jung-Pao Hsieh , Ming-Cheng Chiang
发明人： Jung-Pao Hsieh , Ming-Cheng Chiang
IPC分类号： A63B21/00
CPC分类号： A63B23/12 , A63B21/0004 , A63B21/023 , A63B21/0455 , A63B21/4035 , A63B21/4047 , A63B23/0211 , A63B23/03533 , A63B23/0488
摘要： The combination limb and abdominal exerciser of the present invention has a first torsional spring coupled between two rods of a set of pivotally connected rod members, such that the expansion or compression of the first torsional spring provides an exercise resistance when the two rods are moved outward away from or moved inward closer to each other by an external force, and the two rods return by the resilience of the first torsional spring when the external force is released, so as to help a user to exercise the upper limbs or exercise the lower limbs. Furthermore, a handle can be axially disposed at the end of each of the two rods, and a second torsional spring is disposed between each handle and the corresponding rod. The user can hold the handles and make the rods to rotate with respect to each other for wrist exercise.
摘要翻译：本发明的组合肢体和腹部锻炼者具有联接在一组枢转连接的杆构件的两个杆之间的第一扭转弹簧，使得当两个杆向外移动时，第一扭转弹簧的膨胀或压缩提供运动阻力通过外力离开或靠近彼此移动，并且当外力被释放时，两个杆由第一扭转弹簧的弹性返回，以帮助使用者锻炼上肢或锻炼下肢。此外，手柄可以轴向设置在两个杆中的每一个的端部，并且第二扭转弹簧设置在每个手柄和相应的杆之间。用户可以握住手柄并使杆相对于彼此旋转以进行手腕锻炼。

5. 发明申请

US20100067277A1 Content-Addressable Memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US20100067277A1
公开(公告)日：2010-03-18
申请号：US12561539
申请日：2009-09-17
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G11C15/04
摘要： A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first comparison result; and a first CMOS logic circuit for performing a logic operation on the first comparison result and outputting a first matching result. The second memory unit includes: a second data memory cell for storing a second data bit; a second comparison circuit for comparing a second search bit with the second data bit to determine if there is a match, and outputting a second comparison result; and a second static CMOS logic circuit for performing a logic operation on the first matching result and the second comparison result, and outputting an output matching result.
摘要翻译： CAM包括第一和第二存储器单元。第一存储单元包括：用于存储第一数据位的第一数据存储单元; 第一比较电路，用于将第一搜索位与第一数据位进行比较，以确定是否存在匹配，并输出第一比较结果; 以及第一CMOS逻辑电路，用于对第一比较结果执行逻辑运算并输出第一匹配结果。第二存储器单元包括：用于存储第二数据位的第二数据存储单元; 第二比较电路，用于将第二搜索位与第二数据位进行比较，以确定是否存在匹配，并输出第二比较结果; 以及第二静态CMOS逻辑电路，用于对第一匹配结果和第二比较结果执行逻辑运算，并输出输出匹配结果。

6. 发明申请

US20090310395A1 Content-Addressable Memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US20090310395A1
公开(公告)日：2009-12-17
申请号：US12480101
申请日：2009-06-08
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit.
摘要翻译：内容寻址存储器（CAM）包括第一CAM单元和第二CAM单元。第一CAM单元存储第一数据位，并将第一数据位与第一搜索位进行比较，以确定它们是否匹配。第二CAM单元存储第二数据位，并将第二数据位与第二搜索位进行比较，以确定它们是否匹配。第一CAM单元包括第一逻辑电路，第二CAM单元包括第二逻辑电路，第一逻辑电路和第二逻辑电路形成静态CMOS逻辑电路。

7. 发明授权

US07330075B2 Output impedance control circuit and control method thereof 有权
标题翻译：输出阻抗控制电路及其控制方法
公开(公告)号：US07330075B2
公开(公告)日：2008-02-12
申请号：US11023579
申请日：2004-12-29
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： H03F3/45 , H03F1/30
CPC分类号： H03F1/56 , H03F3/45
摘要： The invention provides an apparatus and a method for adjusting an output impedance of an output stage. The apparatus comprises a detector for outputting a direct current potential corresponding to the impedance of the output stage circuit. It also comprises a controlling unit for outputting a control signal according to the direct current potential and a reference potential, and for adjusting the output impedance of the output stage according to the control signal.
摘要翻译：本发明提供一种用于调节输出级的输出阻抗的装置和方法。该装置包括用于输出对应于输出级电路的阻抗的直流电位的检测器。它还包括用于根据直流电位和参考电位输出控制信号的控制单元，并且用于根据控制信号调整输出级的输出阻抗。

8. 发明授权

US08059440B2 Content-addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08059440B2
公开(公告)日：2011-11-15
申请号：US12480101
申请日：2009-06-08
申请人： Ming-Cheng Chiang
发明人： Ming-Cheng Chiang
IPC分类号： G11C15/00 , G11C8/00
CPC分类号： G11C15/04
摘要： A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit.
摘要翻译：内容寻址存储器（CAM）包括第一CAM单元和第二CAM单元。第一CAM单元存储第一数据位，并将第一数据位与第一搜索位进行比较，以确定它们是否匹配。第二CAM单元存储第二数据位，并将第二数据位与第二搜索位进行比较，以确定它们是否匹配。第一CAM单元包括第一逻辑电路，第二CAM单元包括第二逻辑电路，第一逻辑电路和第二逻辑电路形成静态CMOS逻辑电路。

9. 发明授权

US07701284B2 Line driver capable of automatically adjusting output impedance 有权
标题翻译：线路驱动器能够自动调节输出阻抗
公开(公告)号：US07701284B2
公开(公告)日：2010-04-20
申请号：US12167408
申请日：2008-07-03
申请人： Su-Liang Liao , Ming-Cheng Chiang
发明人： Su-Liang Liao , Ming-Cheng Chiang
IPC分类号： H03F3/45 , H03F1/34
CPC分类号： H03F1/34 , H03F3/45475 , H03F2203/45138 , H03F2203/45522 , H03F2203/45528
摘要： A line driver includes: a differential amplifier for amplifying an input signal to generate an output signal; first and second series resistors coupled respectively to output terminals of the differential amplifier and through which the output signal is output; first and second negative-feedback resistors each coupled between a respective input terminal and a respective output terminal of the differential amplifier; first and second positive-feedback variable resistors each coupled between a respective input terminal of the differential amplifier and a respective one of the first and second series resistors; and an adjusting unit coupled to the first and second positive-feedback variable resistors to adjust a resistance thereof with reference to the output signal.
摘要翻译：线驱动器包括：差分放大器，用于放大输入信号以产生输出信号; 第一和第二串联电阻分别耦合到差分放大器的输出端并输出输出信号; 第一和第二负反馈电阻，每个耦合在差分放大器的相应输入端和相应的输出端之间; 第一和第二正反馈可变电阻器，每个耦合在差分放大器的相应输入端子和第一和第二串联电阻器中的相应一个之间; 以及调节单元，其耦合到所述第一和第二正反馈可变电阻器，以参考所述输出信号调整其电阻。

10. 发明申请

US20090009242A1 LINE DRIVER CAPABLE OF AUTOMATICALLY ADJUSTING OUTPUT IMPEDANCE 有权
标题翻译：能够自动调整输出阻抗的线路驱动器
公开(公告)号：US20090009242A1
公开(公告)日：2009-01-08
申请号：US12167408
申请日：2008-07-03
申请人： Su-Liang LIAO , Ming-Cheng Chiang
发明人： Su-Liang LIAO , Ming-Cheng Chiang
IPC分类号： H03F1/36
CPC分类号： H03F1/34 , H03F3/45475 , H03F2203/45138 , H03F2203/45522 , H03F2203/45528
摘要： A line driver includes: a differential amplifier for amplifying an input signal to generate an output signal; first and second series resistors coupled respectively to output terminals of the differential amplifier and through which the output signal is output; first and second negative-feedback resistors each coupled between a respective input terminal and a respective output terminal of the differential amplifier; first and second positive-feedback variable resistors each coupled between a respective input terminal of the differential amplifier and a respective one of the first and second series resistors; and an adjusting unit coupled to the first and second positive-feedback variable resistors to adjust a resistance thereof with reference to the output signal.
摘要翻译：线驱动器包括：差分放大器，用于放大输入信号以产生输出信号; 第一和第二串联电阻分别耦合到差分放大器的输出端并输出输出信号; 第一和第二负反馈电阻，每个耦合在差分放大器的相应输入端和相应的输出端之间; 第一和第二正反馈可变电阻器，每个耦合在差分放大器的相应输入端子和第一和第二串联电阻器中的相应一个之间; 以及调节单元，其耦合到所述第一和第二正反馈可变电阻器，以参考所述输出信号调整其电阻。

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