专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07781330B2 Method of fabricating a semiconductor device comprising high and low density patterned contacts 失效
标题翻译：制造包括高和低密度图案化触点的半导体器件的方法
公开(公告)号：US07781330B2
公开(公告)日：2010-08-24
申请号：US11878508
申请日：2007-07-25
申请人： Chae-Iyoung Kim , Chang-ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
发明人： Chae-Iyoung Kim , Chang-ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/7688 , Y10S438/947
摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.
摘要翻译：提供制造半导体器件的方法。所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。第一接触掩模层可以形成在第一区域中。第一虚拟掩模层可以形成在第二区域中。可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

2. 发明申请

US20080206985A1 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080206985A1
公开(公告)日：2008-08-28
申请号：US11878508
申请日：2007-07-25
申请人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
发明人： Chae-Iyoung Kim , Chang-Ki Hong , Bo-un Yoon , Sung-ho Shin , Byoung-ho Kwon
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/7688 , Y10S438/947
摘要： Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.
摘要翻译：提供制造半导体器件的方法。所述方法包括在具有第一区域和第二区域的半导体衬底上形成层间绝缘层。第一接触塞可以形成在第二区域的一部分上以填充多个第一接触孔。多个第一接触掩模层和多个第一伪掩模层可以形成在层间绝缘层上。第一接触掩模层可以形成在第一区域中。第一虚拟掩模层可以形成在第二区域中。可以在两个相邻的第一接触掩模层之间形成多个第二接触掩模层。可以在两个相邻的第一虚拟掩模层之间形成多个第二虚拟掩模层。可以使用第一接触掩模层和第二接触掩模层作为蚀刻停止层来蚀刻层间绝缘层，以形成穿过形成在第一区域中的层间绝缘层的多个第二接触孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式