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1. 发明公开

KR20180020943A 픽셀 배열 구조체, 디스플레이 기판, 디스플레이 장치 및 그 제조 방법 审中-公开
标题翻译：像素阵列结构，显示基板，显示装置及其制造方法
公开(公告)号：KR20180020943A
公开(公告)日：2018-02-28
申请号：KR20177022698
申请日：2017-03-08
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： JIN XIAODAN , HUANGFU LUJIANG , LIANG YINAN
IPC分类号： H01L27/32 , H01L51/56
CPC分类号： C23C14/04 , H01L27/32
摘要： 디스플레이디바이스를위한픽셀배열구조체가개시되어있다. 픽셀배열구조체는제1 픽셀및 제2 픽셀을포함할수 있다. 제1 픽셀과제2 픽셀은행 방향및 열방향에서교대로있다. 제1 픽셀및 제2 픽셀각각은제1 서브-픽셀, 제2 서브-픽셀및 제3 서브-픽셀을포함한다. 제1 픽셀에서의제1 서브-픽셀, 제2 서브-픽셀및 제3 서브-픽셀은삼각형분포를형성한다. 제2 픽셀에서의제1 서브-픽셀, 제2 서브-픽셀및 제3 서브-픽셀은제1 픽셀에서의삼각형분포에대해역삼각형분포를형성한다. 제1 픽셀및 제2 픽셀각각에서의제2 서브-픽셀및 제3 서브-픽셀은실질적으로동일한행 상에위치된다.
摘要翻译：公开了一种用于显示装置的像素阵列结构。像素阵列结构可以包括第一像素和第二像素。第一像素任务2在像素库方向和列方向上交替。第一像素和第二像素中的每一个包括第一子像素，第二子像素和第三子像素。第一像素中的第一子像素，第二子像素和第三子像素形成三角形分布。第二像素处的第一子像素，第二子像素和第三子像素形成第一像素处的三角形分布的逆三角分布。第一像素和第二像素中的第二子像素和第三子像素分别位于基本上相同的行上。

2. 发明专利

JP2012252337A Driving apparatus, oled panel and method for driving oled panel 有权
标题翻译：驱动装置，OLED面板和驱动OLED面板的方法
公开(公告)号：JP2012252337A
公开(公告)日：2012-12-20
申请号：JP2012125838
申请日：2012-06-01
申请人： Boe Technology Group Co Ltd , 京東方科技集團股▲ふん▼有限公司
发明人： LIANG YINAN , MA ZHANJIE , LONG CHUNPING , CHENG JUN , SEKI RAI , WANG DONG F , JIANG CHUN-SHENG , YOO JEONG
IPC分类号： G09G3/30 , G09G3/20 , H01L51/50 , H05B33/08
CPC分类号： G09G3/3283 , G09G2310/0248
摘要： PROBLEM TO BE SOLVED: To provide a driving apparatus that can be integrated on a backboard of pixel circuits and is capable of providing fast and stable current driving, and to provide an OLED (Organic Light-Emitting Diode) panel that is driven by the driving apparatus, and a method for driving the OLED panel.SOLUTION: The driving apparatus includes: a switching module for selecting a voltage signal according to a received clock signal; a conversion module for converting the received voltage signal into a current signal; and an output module for outputting the voltage signal or the converted current signal to drive a pixel circuit array, in which the switching module is connected to the conversion module and the output module, and the conversion module is connected to the switching module and the output module.
摘要翻译：要解决的问题：提供可以集成在像素电路的背板上并且能够提供快速和稳定的电流驱动的驱动装置，并且提供被驱动的OLED（有机发光二极管）面板通过驱动装置和用于驱动OLED面板的方法。解决方案：驱动装置包括：切换模块，用于根据所接收的时钟信号选择电压信号; 用于将接收的电压信号转换成电流信号的转换模块; 以及输出模块，用于输出电压信号或转换的电流信号以驱动像素电路阵列，其中开关模块连接到转换模块和输出模块，并且转换模块连接到开关模块和输出端模块。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012244173A Thin-film transistor containing polysilicon active layer, manufacturing method thereof, and array substrate 审中-公开
标题翻译：包含多晶硅活性层的薄膜晶体管，其制造方法和阵列基板
公开(公告)号：JP2012244173A
公开(公告)日：2012-12-10
申请号：JP2012110601
申请日：2012-05-14
申请人： Boe Technology Group Co Ltd , 京東方科技集團股▲ふん▼有限公司
发明人： YOO JEONG , LONG CHUNPING , JIANG CHUN-SHENG , CHENG JUN , SEKI RAI , WANG DONG F , LIANG YINAN
IPC分类号： H01L21/336 , H01L21/20 , H01L29/786
CPC分类号： H01L29/6675 , H01L27/1277
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a thin-film transistor containing a polysilicon active layer.SOLUTION: A manufacturing method of a thin-film transistor containing a polysilicon active layer comprises the steps of: forming an active layer containing a source region, a drain region, and a channel region by depositing an amorphous silicon layer on a substrate and patterning the amorphous silicon layer; depositing induction metals on the source region and the drain region; crystallizing the active layer on which the induction metals are deposited due to the action of the induction metals by performing first heat treatment for the active layer; doping the source region and the drain region with a first impurity for collecting the induction metals; and absorbing the first impurity into the induction metals remaining in the channel region by performing second heat treatment for the doped active layer.
摘要翻译：解决的问题：提供一种含有多晶硅活性层的薄膜晶体管的制造方法。解决方案：包含多晶硅有源层的薄膜晶体管的制造方法包括以下步骤：通过在衬底上沉积非晶硅层来形成包含源极区，漏极区和沟道区的有源层以及图案化所述非晶硅层; 在源极区域和漏极区域上沉积感应金属; 通过对活性层进行第一热处理，由于感应金属的作用而使感应金属沉积在其上沉积的活性层; 用第一杂质掺杂源区和漏区以收集感应金属; 以及通过对掺杂的有源层进行第二热处理，将第一杂质吸收到留在沟道区中的感应金属中。版权所有（C）2013，JPO＆INPIT

4. 发明专利

AU2017408796B9 Display panel, display apparatus, method of detecting crack in sealant layer of display panel, and method of fabricating display panel 未知
公开(公告)号：AU2017408796B9
公开(公告)日：2020-06-25
申请号：AU2017408796
申请日：2017-07-18
申请人： BOE TECHNOLOGY GROUP CO LTD , CHENGDU BOE OPTOELECT TECH CO
发明人： ZHOU ZHENLI , JIANG ZHILIANG , LIANG YINAN
IPC分类号： G09G3/00
摘要： (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property (1) OrganizationIIIIIIIIIIIDIIIIIIIIIDDIIiDIII International Bureau (10) International Publication Number (43) International Publication Date W O 2019/014825 A1 24 January 2019 (24.01.2019) W IP0I PCT (51) International Patent Classification: Minsheng Financial Center, 28 Jianguomennei Avenue, G02F 1/13 (2006.01) G02F 1/1339 (2006.01) Dongcheng District, Beijing 100005 (CN). (21) International Application Number: (81) Designated States (unless otherwise indicated, for every PCT/CN2017/093319 kind ofnational protection available): AE, AG, AL, AM, (22) International Filing Date: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, 18 July 2017 (18.07.2017) CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, Fl, GB, GD, GE, GH, GM, GT, HN, (25) Filing Language: English HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (26) Publication Language• English KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, (71) Applicants: BOE TECHNOLOGY GROUP CO., LTD. OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, Beijing 100015 (CN). CHENGDU BOE OPTOELEC- TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. TRONICS TECHNOLOGY CO., LTD. [CN/CN]; (84) Designated States (unless otherwise indicated, for every No.1188, Hezuo Rd., (West Zone), Hi-tech Development kind of regional protection available): ARIPO (BW, GH, Zone,Chengdu,Sichuan611731(CN). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (72) Inventors: ZHOU, Zhenli; No.9 Dize Rd., BDA, Beijing UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, 100176 (CN). JIANG, Zhiliang; No.9 Dize Rd., BDA, Bei- TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, jing 100176 (CN). LIANG, Yinan; No.9 Dize Rd., BDA, EE, ES, Fl, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, Beijing 100176 (CN). MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, (74) Agent: TEE&HOWE INTELLECTUAL PROPERTY KM, ML, MR, NE, SN, TD, TG). ATTORNEYS; CHEN, Yuan, 10th Floor, Tower D, (54) Title: DISPLAY PANEL, DISPLAY APPARATUS, METHOD OF DETECTING CRACK IN SEALANT LAYER OF DISPLAY PANEL, AND METHOD OF FABRICATING DISPLAY PANEL (57) Abstract: A display panel. The display panel includes a first sub A strate(1); a second substrate(2) facing the first substrate(1); a sealant layer(3) between the first substrate(l) and the second substrate(2) seal ing the first substrate(l) and the second substrate(2) together to form a Sell; and first conductiveline layer(4) having a first continuous con ductive line configured to detect crack in the sealant layer(3). The first -conductive line layer(4) is incontact with the sealant layer(3). - 5 -, 4 - ,3 W O 2019/014825 A25Al|||||||||||||||||||||||||||||||||||||||||||||||||||| Published: - with international search report (Art. 21(3))

5. 发明专利

RU2738785C1 ПАНЕЛЬ ОТОБРАЖЕНИЯ, УСТРОЙСТВО ОТОБРАЖЕНИЯ, СПОСОБ ОБНАРУЖЕНИЯ ТРЕЩИНЫ В ГЕРМЕТИЗИРУЮЩЕМ СЛОЕ ПАНЕЛИ ОТОБРАЖЕНИЯ И СПОСОБ ИЗГОТОВЛЕНИЯ ПАНЕЛИ ОТОБРАЖЕНИЯ 未知
公开(公告)号：RU2738785C1
公开(公告)日：2020-12-16
申请号：RU2018135974
申请日：2017-07-18
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： ZHOU ZHENLI , JIANG ZHILIANG , LIANG YINAN
IPC分类号： G02F1/13
摘要： Изобретениеотноситсяк технологиямотображения, вчастностик панелиотображения. Панельотображениявключаетв себяпервуюподложку; вторуюподложку, обращеннуюк первойподложке; герметизирующийслоймеждупервойподложкойи второйподложкой, совместногерметизирующийпервуюподложкуи вторуюподложку, чтобысформироватьячейку; ипервыйслойэлектропроводныхлиний, имеющийпервуюнепрерывнуюэлектропроводнуюлинию, выполненнуюс возможностьюобнаруживатьтрещинув герметизирующемслое. Первыйслойэлектропроводныхлинийнаходитсяв контактес герметизирующимслоем. Изобретениепозволяетповыситьэффективностьобнаружениятрещин. 5 н. и 15 з.п. ф-лы, 7 ил.

6. 发明专利

AU2017408796B2 Display panel, display apparatus, method of detecting crack in sealant layer of display panel, and method of fabricating display panel 未知
公开(公告)号：AU2017408796B2
公开(公告)日：2020-01-23
申请号：AU2017408796
申请日：2017-07-18
申请人： BOE TECHNOLOGY GROUP CO LTD , CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO LTD
发明人： ZHOU ZHENLI , JIANG ZHILIANG , LIANG YINAN
IPC分类号： G09G3/00
摘要： The present application discloses a display panel. The display panel includes a first substrate; a second substrate facing the first substrate; a sealant layer between the first substrate and the second substrate sealing the first substrate and the second substrate together to form a cell; and a first conductive line layer having a first continuous conductive line configured to detect crack in the sealant layer. The first conductive line layer is in contact with the sealant layer.

7. 发明专利

AU2017408796A1 Display panel, display apparatus, method of detecting crack in sealant layer of display panel, and method of fabricating display panel 未知
公开(公告)号：AU2017408796A1
公开(公告)日：2019-02-07
申请号：AU2017408796
申请日：2017-07-18
申请人： BOE TECHNOLOGY GROUP CO LTD , CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO LTD
发明人： ZHOU ZHENLI , JIANG ZHILIANG , LIANG YINAN
IPC分类号： G09G3/00
摘要： The present application discloses a display panel. The display panel includes a first substrate; a second substrate facing the first substrate; a sealant layer between the first substrate and the second substrate sealing the first substrate and the second substrate together to form a cell; and a first conductive line layer having a first continuous conductive line configured to detect crack in the sealant layer. The first conductive line layer is in contact with the sealant layer.

8. 发明公开

EP2869329A4 THIN-FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：EP2869329A4
公开(公告)日：2016-03-02
申请号：EP12844652
申请日：2012-11-13
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： LIANG YINAN
IPC分类号： H01L21/02 , H01L21/336 , H01L21/77 , H01L29/786
CPC分类号： H01L21/02672 , H01L21/02532 , H01L27/1277 , H01L29/66757 , H01L29/78675

9. 发明公开

EP2985784A4 LOW-TEMPERATURE POLY-SILICON TFT ARRAY SUBSTRATE, MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS 有权
标题翻译：多晶硅TFT低温阵列基板及其制造方法其显示装置
公开(公告)号：EP2985784A4
公开(公告)日：2017-03-08
申请号：EP14882781
申请日：2014-09-30
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： LONG CHUNPING , LIANG YINAN , LIU ZHENG , WANG ZUQIANG , TIAN XUEYAN
IPC分类号： H01L27/12
CPC分类号： H01L27/1288 , H01L27/1255 , H01L27/3262 , H01L2227/323
摘要： The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

10. 发明公开

EP3185305A4 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE 有权
公开(公告)号：EP3185305A4
公开(公告)日：2018-04-11
申请号：EP14882777
申请日：2014-12-17
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： LONG CHUNPING , LIANG YINAN
IPC分类号： H01L29/786 , H01L21/3213 , H01L27/12 , H01L27/32 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66
CPC分类号： H01L29/78675 , H01L21/02532 , H01L21/02595 , H01L21/0273 , H01L21/26513 , H01L21/283 , H01L21/3065 , H01L21/32139 , H01L23/3171 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1288 , H01L27/3262 , H01L27/3276 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/4958 , H01L29/66757 , H01L29/786 , H01L29/78618 , H01L29/78633 , H01L2227/323
摘要： A thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The thin film transistor includes a gate electrode (7), a source electrode (9), a drain electrode (10), an active layer (4) and a gate insulation layer (6). The gate insulation layer (6) is provided above the active layer (4), the gate (7), the source electrode (9) and the drain electrode (10) are provided on a same layer above the gate insulation layer (6), the active layer (4) and the source electrode (9) are connected through a first connection electrode (12b), and the active layer and the drain electrode are connected through a second connection electrode (12c). The thin film transistor can be formed by three times of patterning processes, by which the process time period is shortened, the process yield is improved, and the process cost is reduced, and so on.

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